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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-15 08:29:10 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | f858219c4ed18fb5886641efd1e71f5aad0b1c84 (patch) | |
| tree | d1d7f73c52a0bfe646b46dcf7947b51701480e3f /tests/arch | |
| parent | 717fb492b35a93ae78e33f742d8c3d493be7e4e8 (diff) | |
| download | yosys-f858219c4ed18fb5886641efd1e71f5aad0b1c84.tar.gz yosys-f858219c4ed18fb5886641efd1e71f5aad0b1c84.tar.bz2 yosys-f858219c4ed18fb5886641efd1e71f5aad0b1c84.zip | |
Cleanup tests
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/xilinx/bug1480.ys | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/arch/xilinx/bug1480.ys b/tests/arch/xilinx/bug1480.ys new file mode 100644 index 000000000..84faea08a --- /dev/null +++ b/tests/arch/xilinx/bug1480.ys @@ -0,0 +1,18 @@ +read_verilog << EOF +module top(...); + +input signed [17:0] A; +input signed [17:0] B; +output X; +output Y; + +wire [35:0] P; +assign P = A * B; + +assign X = P[0]; +assign Y = P[35]; + +endmodule +EOF + +synth_xilinx |