| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 14 | -92/+961 | |
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| | * | | | | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 1 | -4/+3 | |
| | * | | | | | | abc9 to perform new 'map_ffs' before 'map_luts' | Eddie Hung | 2019-08-21 | 1 | -3/+18 | |
| | * | | | | | | Add init support | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
| * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-28 | 13 | -249/+865 | |
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| | * | | | | | | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor | Eddie Hung | 2019-08-28 | 1 | -3/+8 | |
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| | * | | | | | Merge pull request #1332 from YosysHQ/dave/ecp5gsr | David Shah | 2019-08-28 | 6 | -54/+212 | |
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| | | * | | | | | ecp5: Add GSR support | David Shah | 2019-08-27 | 6 | -54/+212 | |
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| | * | | | | | xilinx: Add SRLC16E primitive. | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+21 | |
| | * | | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 1 | -0/+8 | |
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| | | * | | | | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 | |
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| | * | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | * | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 3 | -18/+36 | |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 29 | -299/+1059 | |
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| | * | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 6 | -283/+537 | |
| | * | | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+1 | |
| | * | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -18/+27 | |
| | * | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 6 | -71/+220 | |
| * | | | | | | Fix spacing | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
| * | | | | | | Remove unused model | Eddie Hung | 2019-08-23 | 1 | -13/+0 | |
| * | | | | | | Put attributes above port | Eddie Hung | 2019-08-23 | 2 | -27/+62 | |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 17 | -102/+981 | |
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| | * | | | | | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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| | * | | | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 3 | -14/+28 | |
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| | * | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 | |
| | * | | | Merge pull request #1289 from mmicko/anlogic_fixes | Clifford Wolf | 2019-08-22 | 5 | -91/+162 | |
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| | | * \ \ | Merge remote-tracking branch 'upstream/master' into anlogic_fixes | Miodrag Milanovic | 2019-08-18 | 7 | -165/+37 | |
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| | | * | | | | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 5 | -91/+162 | |
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| | * | | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 | |
| | * | | | | Merge pull request #1281 from mmicko/efinix | Clifford Wolf | 2019-08-22 | 9 | -0/+798 | |
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| | | * | | | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
| | | * | | | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 | |
| | | * | | | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 | |
| | | * | | | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 | |
| | | * | | | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
| | | * | | | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 | |
| | | * | | | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 | |
| | | * | | | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 | |
| | | * | | | Merge remote-tracking branch 'upstream/master' into efinix | Miodrag Milanovic | 2019-08-09 | 9 | -267/+303 | |
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| | | * | | | | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 | |
| | | * | | | | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 | |
| | | * | | | | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 | |
| | | * | | | | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 | |
| * | | | | | | Use semicolon | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
| * | | | | | | techmap before read | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
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| | * | | | | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
| * | | | | | | Add abc_arrival to SRL* | Eddie Hung | 2019-08-21 | 1 | -3/+5 | |
| * | | | | | | Oops | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
| * | | | | | | xilinx to use abc_map.v with -max_iter 1 | Eddie Hung | 2019-08-20 | 6 | -171/+26 | |
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index : iCE40/yosys | |
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