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| author | Marcin Kościelnicki <koriakin@0x04.net> | 2019-08-13 18:05:49 +0000 |
|---|---|---|
| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2019-08-13 18:05:49 +0000 |
| commit | 49765ec19ea63bff5f04e28e5729d5852a2f8287 (patch) | |
| tree | 46b0c8b11c8d2c9f081fa3cac7057b7a9ef8ed08 /techlibs | |
| parent | c6d5b97b98e6edc395ee14ad60430f7ebc264f01 (diff) | |
| download | yosys-49765ec19ea63bff5f04e28e5729d5852a2f8287.tar.gz yosys-49765ec19ea63bff5f04e28e5729d5852a2f8287.tar.bz2 yosys-49765ec19ea63bff5f04e28e5729d5852a2f8287.zip | |
minor review fixes
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e9e8dbfea..4069094a6 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -64,7 +64,7 @@ struct SynthXilinxPass : public ScriptPass log(" (this feature is experimental and incomplete)\n"); log("\n"); log(" -ise\n"); - log(" generate an output netlist suitable for ISE\n"); + log(" generate an output netlist suitable for ISE (enables -iopad)\n"); log("\n"); log(" -nobram\n"); log(" disable inference of block rams\n"); |