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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 11:39:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 11:39:14 -0700 |
| commit | 8f69be9cc70191e14e87b7a0f03ea08a572ac33c (patch) | |
| tree | dc07a4fe52c3233895adbdfd7c6facc3d85fe562 /techlibs | |
| parent | 399ac760ff2bf4a7d438ed388820e7bfb511de6b (diff) | |
| parent | 076af2e6176ecc440be7b7fa984ea5b461bb95de (diff) | |
| download | yosys-8f69be9cc70191e14e87b7a0f03ea08a572ac33c.tar.gz yosys-8f69be9cc70191e14e87b7a0f03ea08a572ac33c.tar.bz2 yosys-8f69be9cc70191e14e87b7a0f03ea08a572ac33c.zip | |
Merge remote-tracking branch 'origin/master' into xaig_arrival
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/synth.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 555de9fba..a176357a7 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -175,7 +175,7 @@ struct SynthPass : public ScriptPass log_cmd_error("This command only operates on fully selected designs!\n"); if (abc == "abc9" && !lut) - log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)"); + log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n"); log_header(design, "Executing SYNTH pass.\n"); log_push(); |