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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 13:05:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 13:05:10 -0700 |
| commit | 5ce0c31d0e01603264b23cff8f6d431902f08b63 (patch) | |
| tree | f73865a3ede084fb0b1c2f343af06c8551aa725e /techlibs | |
| parent | df53fe12e7ed667d36d3829681cfc43a3355b834 (diff) | |
| download | yosys-5ce0c31d0e01603264b23cff8f6d431902f08b63.tar.gz yosys-5ce0c31d0e01603264b23cff8f6d431902f08b63.tar.bz2 yosys-5ce0c31d0e01603264b23cff8f6d431902f08b63.zip | |
Add init support
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7ba67409b..49f32002c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -406,7 +406,7 @@ struct SynthXilinxPass : public ScriptPass // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming if (!nosrl || help_mode) - run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); + run("xilinx_srl -minlen 3", "(skip if '-nosrl')"); run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); |