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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 17:34:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 17:34:40 -0700 |
| commit | 15188033da68c89c409af0839f22e6acc573abb7 (patch) | |
| tree | 26cd2808fbcedddf0d86d071edcb17de432c6a7c /techlibs | |
| parent | 6d76ae4c65d3a7b403888219900a3c0f85ee737d (diff) | |
| download | yosys-15188033da68c89c409af0839f22e6acc573abb7.tar.gz yosys-15188033da68c89c409af0839f22e6acc573abb7.tar.bz2 yosys-15188033da68c89c409af0839f22e6acc573abb7.zip | |
Add variable length support to xilinx_srl
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 2c5f2ec57..8bf43bf97 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -352,9 +352,8 @@ struct SynthXilinxPass : public ScriptPass if (!nosrl || help_mode) { // shregmap operates on bit-level flops, not word-level, // so break those down here - run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')"); - // shregmap with '-tech xilinx' infers variable length shift regs - run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); + run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')"); + run("xilinx_srl -variable -minlen 3", "(skip if '-nosrl')"); } std::string techmap_args = " -map +/techmap.v"; @@ -414,7 +413,7 @@ struct SynthXilinxPass : public ScriptPass // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming if (!nosrl || help_mode) - run("xilinx_srl -minlen 3", "(skip if '-nosrl')"); + run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')"); std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"; if (help_mode) |