| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-12 | 4 | -177/+172 |
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| | * | Remove extra newline | Eddie Hung | 2019-06-03 | 1 | -1/+0 |
| | * | Execute techmap and arith_map simultaneously | Eddie Hung | 2019-06-03 | 1 | -6/+6 |
| | * | Add "min bits" and "min wports" to xilinx dram rules | Eddie Hung | 2019-05-23 | 1 | -0/+4 |
| | * | Add "stat -tech xilinx" | Clifford Wolf | 2019-05-11 | 1 | -1/+1 |
| | * | Add "synth_xilinx -arch" | Clifford Wolf | 2019-05-07 | 1 | -1/+13 |
| | * | Rename cells_map.v to prevent clash with ff_map.v | Eddie Hung | 2019-05-03 | 1 | -6/+8 |
| | * | Back to passing all xc7srl tests! | Eddie Hung | 2019-05-01 | 1 | -5/+4 |
| | * | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine | Eddie Hung | 2019-05-01 | 1 | -165/+97 |
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| | | * | Refactor synth_xilinx to auto-generate doc | Eddie Hung | 2019-04-26 | 1 | -153/+95 |
| | * | | WIP | Eddie Hung | 2019-04-28 | 1 | -36/+22 |
| | * | | Move neg-pol to pos-pol mapping from ff_map to cells_map.v | Eddie Hung | 2019-04-28 | 2 | -9/+12 |
| | * | | Revert synth_xilinx 'fine' label more to how it used to be... | Eddie Hung | 2019-04-26 | 1 | -21/+40 |
| | * | | Where did this check come from!?! | Eddie Hung | 2019-04-26 | 1 | -1/+0 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 6 | -36/+222 |
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| | * | Update help message | Eddie Hung | 2019-04-22 | 1 | -1/+1 |
| | * | Move 'shregmap -tech xilinx' into map_cells | Eddie Hung | 2019-04-22 | 1 | -17/+20 |
| | * | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-04-22 | 1 | -0/+2 |
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| | * | | Tidy up, fix for -nosrl | Eddie Hung | 2019-04-21 | 2 | -12/+16 |
| | * | | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-21 | 1 | -2/+2 |
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| | * | | | Add comments | Eddie Hung | 2019-04-21 | 1 | -0/+7 |
| | * | | | Use new pmux2shiftx from #944, remove my old attempt | Eddie Hung | 2019-04-21 | 1 | -3/+8 |
| | * | | | Merge remote-tracking branch 'origin' into xc7srl | Eddie Hung | 2019-04-20 | 3 | -41/+60 |
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| | * | | | | Call shregmap twice -- once for variable, another for fixed | Eddie Hung | 2019-04-05 | 2 | -8/+14 |
| | * | | | | Move dffinit til after abc | Eddie Hung | 2019-04-05 | 3 | -2/+2 |
| | * | | | | Merge branch 'eddie/fix_retime' into xc7srl | Eddie Hung | 2019-04-05 | 4 | -11/+12 |
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| | * | | | | | techmap inside map_cells stage | Eddie Hung | 2019-04-05 | 2 | -2/+1 |
| | * | | | | | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-04 | 1 | -0/+1 |
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| | * | | | | | | Use soft-logic, not LUT3 instantiation | Eddie Hung | 2019-04-04 | 1 | -4/+2 |
| | * | | | | | | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-04 | 1 | -12/+12 |
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| | * | | | | | | | Cleanup comments | Eddie Hung | 2019-04-04 | 1 | -5/+4 |
| | * | | | | | | | t:$dff* -> t:$dff t:$dffe | Eddie Hung | 2019-04-04 | 1 | -2/+2 |
| | * | | | | | | | -nosrl meant when -nobram | Eddie Hung | 2019-04-03 | 1 | -1/+1 |
| | * | | | | | | | Remove duplicate STARTUPE2 | Eddie Hung | 2019-04-03 | 1 | -1/+0 |
| | * | | | | | | | Disable shregmap in synth_xilinx if -retime | Eddie Hung | 2019-04-03 | 1 | -3/+3 |
| | * | | | | | | | synth_xilinx to use shregmap with -minlen 3 | Eddie Hung | 2019-03-25 | 1 | -2/+2 |
| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-22 | 2 | -24/+31 |
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| | * | | | | | | | | Add '-nosrl' option to synth_xilinx | Eddie Hung | 2019-03-21 | 1 | -6/+16 |
| | * | | | | | | | | Fine tune cells_map.v | Eddie Hung | 2019-03-20 | 1 | -19/+15 |
| | * | | | | | | | | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length | Eddie Hung | 2019-03-19 | 1 | -53/+20 |
| | * | | | | | | | | Add support for variable length Xilinx SRL > 128 | Eddie Hung | 2019-03-19 | 1 | -11/+67 |
| | * | | | | | | | | Restore original synth_xilinx commands | Eddie Hung | 2019-03-19 | 1 | -1/+2 |
| | * | | | | | | | | Fix spacing | Eddie Hung | 2019-03-19 | 1 | -1/+1 |
| | * | | | | | | | | Fix INIT for variable length SRs that have been bumped up one | Eddie Hung | 2019-03-19 | 1 | -1/+1 |
| | * | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-19 | 1 | -2/+4 |
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| | * | | | | | | | | | Only accept <128 for variable length, only if $shiftx exclusive | Eddie Hung | 2019-03-16 | 1 | -5/+1 |
| | * | | | | | | | | | Cleanup synth_xilinx | Eddie Hung | 2019-03-15 | 2 | -3/+2 |
| | * | | | | | | | | | Working | Eddie Hung | 2019-03-15 | 2 | -47/+78 |
| | * | | | | | | | | | Reverse bits in INIT parameter for Xilinx, since MSB is shifted first | Eddie Hung | 2019-03-14 | 1 | -16/+32 |
| | * | | | | | | | | | Misspell | Eddie Hung | 2019-03-14 | 1 | -1/+1 |
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index : iCE40/yosys | |
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