| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Add '-nosrl' option to synth_xilinx | Eddie Hung | 2019-03-21 | 1 | -6/+16 | |
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| * | | Fine tune cells_map.v | Eddie Hung | 2019-03-20 | 1 | -19/+15 | |
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| * | | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length | Eddie Hung | 2019-03-19 | 1 | -53/+20 | |
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| * | | Add support for variable length Xilinx SRL > 128 | Eddie Hung | 2019-03-19 | 1 | -11/+67 | |
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| * | | Restore original synth_xilinx commands | Eddie Hung | 2019-03-19 | 1 | -1/+2 | |
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| * | | Fix spacing | Eddie Hung | 2019-03-19 | 1 | -1/+1 | |
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| * | | Fix INIT for variable length SRs that have been bumped up one | Eddie Hung | 2019-03-19 | 1 | -1/+1 | |
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| * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-19 | 1 | -2/+4 | |
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| | * | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 | Clifford Wolf | 2019-03-19 | 1 | -2/+4 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Only accept <128 for variable length, only if $shiftx exclusive | Eddie Hung | 2019-03-16 | 1 | -5/+1 | |
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| * | | Cleanup synth_xilinx | Eddie Hung | 2019-03-15 | 2 | -3/+2 | |
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| * | | Working | Eddie Hung | 2019-03-15 | 2 | -47/+78 | |
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| * | | Reverse bits in INIT parameter for Xilinx, since MSB is shifted first | Eddie Hung | 2019-03-14 | 1 | -16/+32 | |
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| * | | Misspell | Eddie Hung | 2019-03-14 | 1 | -1/+1 | |
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| * | | Revert "Add shregmap -init_msb_first and use in synth_xilinx" | Eddie Hung | 2019-03-14 | 1 | -3/+2 | |
| | | | | | | | | | This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75. | |||||
| * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-14 | 10 | -177/+571 | |
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| | * | Merge pull request #842 from litghost/merge_upstream | Clifford Wolf | 2019-03-05 | 10 | -176/+570 | |
| | |\ | | | | | | | Changes required for VPR place and route in synth_xilinx | |||||
| | | * | Revert BRAM WRITE_MODE changes. | Keith Rothman | 2019-03-04 | 1 | -12/+12 | |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | | * | Revert FF models to include IS_x_INVERTED parameters. | Keith Rothman | 2019-03-01 | 1 | -6/+34 | |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | | * | Use singular for disabling of DRAM or BRAM inference. | Keith Rothman | 2019-03-01 | 1 | -13/+13 | |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | | * | Modify arguments to match existing style. | Keith Rothman | 2019-03-01 | 1 | -6/+6 | |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | | * | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 11 | -221/+587 | |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | | Use "write_edif -pvector bra" for Xilinx EDIF files | Clifford Wolf | 2019-03-05 | 1 | -1/+1 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add shregmap -init_msb_first and use in synth_xilinx | Eddie Hung | 2019-03-14 | 1 | -2/+2 | |
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| * | | Fix cells_map for SRL | Eddie Hung | 2019-03-14 | 1 | -19/+17 | |
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| * | | Move shregmap until after first techmap | Eddie Hung | 2019-03-13 | 1 | -2/+2 | |
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| * | | Refactor $__SHREG__ in cells_map.v | Eddie Hung | 2019-03-13 | 1 | -32/+24 | |
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| * | | Remove SRL16/32 from cells_xtra | Eddie Hung | 2019-02-28 | 2 | -18/+2 | |
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| * | | Add SRL16 and SRL32 sim models | Eddie Hung | 2019-02-28 | 1 | -0/+39 | |
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| * | | Fix SRL16/32 techmap off-by-one | Eddie Hung | 2019-02-28 | 1 | -18/+24 | |
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| * | | synth_xilinx to call shregmap with enable support | Eddie Hung | 2019-02-28 | 2 | -24/+29 | |
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| * | | synth_xilinx to use shregmap with -params too | Eddie Hung | 2019-02-28 | 2 | -22/+19 | |
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| * | | synth_xilinx to now have shregmap call after dff2dffe | Eddie Hung | 2019-02-28 | 1 | -0/+2 | |
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| * | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 | Eddie Hung | 2019-02-28 | 1 | -0/+71 | |
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| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -1/+1 | |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | |||||
| * | Add support for Xilinx PS7 block | Eddie Hung | 2018-11-10 | 2 | -0/+624 | |
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| * | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. | Tim 'mithro' Ansell | 2018-10-08 | 1 | -3/+2 | |
| | | | | | | Then if targeting vpr map all the Xilinx specific LUTs back into generic Yosys LUTs. | |||||
| * | Add inout ports to cells_xtra.v | Clifford Wolf | 2018-10-04 | 2 | -2/+14 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | xilinx: Adding missing inout IO port to IOBUF | Tim Ansell | 2018-10-03 | 1 | -0/+1 | |
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| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 | |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | |||||
| * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 2 | -3/+36 | |
| | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`. | |||||
| * | Squelch trailing whitespace, including meta-whitespace | Larry Doolittle | 2018-03-11 | 1 | -8/+8 | |
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| * | Add Xilinx RAM64X1D and RAM128X1D simulation models | Clifford Wolf | 2018-03-07 | 4 | -23/+30 | |
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| * | Add techlibs/xilinx/lut2lut.v | Clifford Wolf | 2017-07-10 | 2 | -0/+66 | |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 | |
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| * | Added black box modules for all the 7-series design elements (as listed in ↵ | Clifford Wolf | 2016-03-19 | 4 | -0/+3441 | |
| | | | | | ug953) | |||||
| * | Run dffsr2dff in synth_xilinx | Clifford Wolf | 2016-02-13 | 1 | -0/+2 | |
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| * | Added "abc -luts" option, Improved Xilinx logic mapping | Clifford Wolf | 2016-02-01 | 1 | -2/+2 | |
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| * | Bugfix in Xilinx LUT mapping | Clifford Wolf | 2015-10-30 | 1 | -1/+1 | |
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| * | Added examples/ top-level directory | Clifford Wolf | 2015-10-13 | 7 | -77/+0 | |
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index : iCE40/yosys | |
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