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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-30 13:58:03 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-30 13:58:03 +0100 |
| commit | 864808992be407a9b33f222fa5846f5cd5f149ea (patch) | |
| tree | d441ce8e388877e033ab9b75ae403fb83f31002c /techlibs/xilinx | |
| parent | 1e32e4bdae2e3fb3d1bf68314e146052a3c65561 (diff) | |
| download | yosys-864808992be407a9b33f222fa5846f5cd5f149ea.tar.gz yosys-864808992be407a9b33f222fa5846f5cd5f149ea.tar.bz2 yosys-864808992be407a9b33f222fa5846f5cd5f149ea.zip | |
Bugfix in Xilinx LUT mapping
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ee67beba7..fbcc96014 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -204,7 +204,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "map_luts")) { - Pass::call(design, "abc -lut 5:8" + string(retime ? " -dff" : "")); + Pass::call(design, "abc -lut 6:8" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); } |