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* Fix for A_WIDTH == 2 but B_WIDTH==3Eddie Hung2019-04-221-1/+1
* Trim A_WIDTH by Y_WIDTH-1Eddie Hung2019-04-221-1/+1
* Add commentEddie Hung2019-04-221-0/+3
* Fix for mux_case_* mappingsEddie Hung2019-04-221-17/+9
* Fix for non-pow2 width muxesEddie Hung2019-04-221-9/+18
* Add synth_xilinx -nomux optionEddie Hung2019-04-222-4/+18
* Cleanup, call pmux2shiftx even without -nosrlEddie Hung2019-04-226-45/+30
* Merge remote-tracking branch 'origin/xc7srl' into xc7muxEddie Hung2019-04-226-31/+216
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| * Update help messageEddie Hung2019-04-221-1/+1
| * Move 'shregmap -tech xilinx' into map_cellsEddie Hung2019-04-221-17/+20
| * Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-221-0/+2
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| | * Re-added clean after techmap in synth_xilinxClifford Wolf2019-04-221-0/+2
| * | Tidy up, fix for -nosrlEddie Hung2019-04-212-12/+16
| * | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-211-2/+2
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| | * Merge branch 'master' into map_cells_before_map_lutsEddie Hung2019-04-215-56/+76
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| * | | Add commentsEddie Hung2019-04-211-0/+7
| * | | Use new pmux2shiftx from #944, remove my old attemptEddie Hung2019-04-211-3/+8
| * | | Merge remote-tracking branch 'origin' into xc7srlEddie Hung2019-04-203-41/+60
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| | * | Revert "synth_* with -retime option now calls abc with -D 1 as well"Eddie Hung2019-04-181-2/+2
| | * | Merge branch 'master' into eddie/fix_retimeEddie Hung2019-04-183-41/+60
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| | * | | synth_* with -retime option now calls abc with -D 1 as wellEddie Hung2019-04-101-2/+2
| * | | | Call shregmap twice -- once for variable, another for fixedEddie Hung2019-04-052-8/+14
| * | | | Move dffinit til after abcEddie Hung2019-04-053-2/+2
| * | | | Merge branch 'eddie/fix_retime' into xc7srlEddie Hung2019-04-054-11/+12
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| | * | | Move techamp t:$_DFF_?N? to before abc callEddie Hung2019-04-051-2/+2
| | * | | RetryEddie Hung2019-04-051-1/+1
| | * | | Resolve @daveshah1 comment, update synth_xilinx helpEddie Hung2019-04-052-7/+9
| | * | | synth_xilinx to techmap FFs after abc call, otherwise -retime failsEddie Hung2019-04-051-3/+3
| * | | | techmap inside map_cells stageEddie Hung2019-04-052-2/+1
| * | | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
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| | * | | Missing techmap entry in helpEddie Hung2019-04-041-0/+1
| * | | | Use soft-logic, not LUT3 instantiationEddie Hung2019-04-041-4/+2
| * | | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-12/+12
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| | * | | synth_xilinx to map_cells before map_lutsEddie Hung2019-04-041-12/+12
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| * | | Cleanup commentsEddie Hung2019-04-041-5/+4
| * | | t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
| * | | -nosrl meant when -nobramEddie Hung2019-04-031-1/+1
| * | | Remove duplicate STARTUPE2Eddie Hung2019-04-031-1/+0
| * | | Disable shregmap in synth_xilinx if -retimeEddie Hung2019-04-031-3/+3
| * | | synth_xilinx to use shregmap with -minlen 3Eddie Hung2019-03-251-2/+2
| * | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-222-24/+31
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| * | | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
| * | | Fine tune cells_map.vEddie Hung2019-03-201-19/+15
| * | | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable lengthEddie Hung2019-03-191-53/+20
| * | | Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-191-11/+67
| * | | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
| * | | Fix spacingEddie Hung2019-03-191-1/+1
| * | | Fix INIT for variable length SRs that have been bumped up oneEddie Hung2019-03-191-1/+1
| * | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-191-2/+4
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| * | | | Only accept <128 for variable length, only if $shiftx exclusiveEddie Hung2019-03-161-5/+1
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