| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model | gatecat | 2023-04-06 | 1 | -160/+30 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Add iopad_external_pin to some basic io primitives | Miodrag Milanovic | 2023-03-20 | 1 | -0/+1 |
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| * | Add missing parameters for ecp5 | Rick Luiken | 2022-04-25 | 1 | -0/+1 |
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| * | ecp5: Do not use specify in generate in cells_sim.v. | Marcelina Kościelnicka | 2022-02-21 | 1 | -28/+15 |
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| * | ecp5: Fix DPR16X4 sim model. | Marcelina Kościelnicka | 2022-02-09 | 1 | -1/+1 |
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| * | ecp5: TRELLIS_FF bypass path only in async mode | Eddie Hung | 2020-05-14 | 1 | -8/+8 |
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| * | xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells | Eddie Hung | 2020-05-14 | 1 | -3/+26 |
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| * | ecp5: (* abc9_flop *) gated behind YOSYS | Eddie Hung | 2020-05-14 | 1 | -0/+2 |
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| * | ecp5: add synth_ecp5 -dff to work with -abc9 | Eddie Hung | 2020-05-14 | 1 | -0/+21 |
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| * | ecp5: remove small LUT entries | Eddie Hung | 2020-02-27 | 1 | -24/+6 |
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| * | ecp5: deprecate abc9_{arrival,required} and *.{lut,box} | Eddie Hung | 2020-02-27 | 1 | -5/+108 |
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| * | Nitpick cleanup for ecp5 | Eddie Hung | 2019-12-27 | 1 | -10/+2 |
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| * | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -6/+6 |
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| * | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-09-02 | 1 | -6/+7 |
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| | * | Fix TRELLIS_FF simulation model | Miodrag Milanovic | 2019-08-31 | 1 | -6/+7 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-30 | 1 | -53/+6 |
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| | * | ecp5: Add simulation equivalence check for Diamond FF implementations | David Shah | 2019-08-30 | 1 | -0/+4 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives. | whitequark | 2019-08-30 | 1 | -55/+2 |
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| | * | ecp5: add missing FD primitives. | whitequark | 2019-08-30 | 1 | -36/+38 |
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| | * | ecp5: fix CEMUX on IFS/OFS primitives. | whitequark | 2019-08-30 | 1 | -9/+9 |
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| * | | Fix spacing | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 1 | -3/+6 |
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| | * | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 1 | -5/+10 |
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| * | | ecp5 to use -max_iter 1 | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| * | | ecp5 to use abc_map.v and _unmap.v | Eddie Hung | 2019-08-20 | 1 | -4/+3 |
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| * | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -2/+2 |
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| * | Update abc_* attr in ecp5 and ice40 | Eddie Hung | 2019-08-16 | 1 | -9/+13 |
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| * | ecp5: Make cells_sim.v consistent with nextpnr | David Shah | 2019-08-07 | 1 | -101/+244 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Disable boxing of ECP5 dist RAM due to regression | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| * | Add write address to abc_scc_break of ECP5 dist RAM | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| * | Refactor for one "abc_carry" attribute on module | Eddie Hung | 2019-06-27 | 1 | -5/+3 |
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| * | Merge origin/master | Eddie Hung | 2019-06-27 | 1 | -41/+53 |
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| * | Add WE to ECP5 dist RAM's abc_scc_break too | Eddie Hung | 2019-06-26 | 1 | -1/+1 |
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| * | Re-enable dist RAM boxes for ECP5 | Eddie Hung | 2019-06-24 | 1 | -1/+1 |
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| * | Revert "Re-enable dist RAM boxes for ECP5" | Eddie Hung | 2019-06-24 | 1 | -1/+1 |
| | | | | | This reverts commit ca0225fcfaa8c9c68647034351a1569464959edf. | ||||
| * | Re-enable dist RAM boxes for ECP5 | Eddie Hung | 2019-06-24 | 1 | -1/+1 |
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| * | Comment out dist RAM boxing on ECP5 for now | Eddie Hung | 2019-06-14 | 1 | -1/+1 |
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| * | Remove WIP ABC9 flop support | Eddie Hung | 2019-06-14 | 1 | -3/+3 |
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| * | ecp5: Add abc9 option | David Shah | 2019-06-14 | 1 | -11/+21 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Fix ECP5 cells_sim for iverilog | Miodrag Milanovic | 2019-03-01 | 1 | -2/+3 |
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| * | Merge pull request #794 from daveshah1/ecp5improve | Clifford Wolf | 2019-02-28 | 1 | -7/+33 |
| |\ | | | | | ECP5 Improvements | ||||
| | * | ecp5: Compatibility with Migen AsyncResetSynchronizer | David Shah | 2019-02-25 | 1 | -0/+17 |
| | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| | * | ecp5: Add LSRMODE to flipflops for PRLD support | David Shah | 2019-01-21 | 1 | -7/+16 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Clean up some whitepsace outliers | Larry Doolittle | 2019-02-26 | 1 | -2/+2 |
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| * | ecp5: Adding some blackbox cells | David Shah | 2018-11-07 | 1 | -1/+1 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ecp5: Sim model fixes | David Shah | 2018-10-19 | 1 | -3/+5 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ecp5: First BRAM type maps successfully | David Shah | 2018-10-10 | 1 | -0/+2 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ecp5: Script for BRAM IO connections | David Shah | 2018-10-10 | 1 | -64/+64 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ecp5: Adding BRAM initialisation and config | David Shah | 2018-10-09 | 1 | -0/+4 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ecp5: Add blackbox for DP16KD | David Shah | 2018-10-05 | 1 | -0/+93 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
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index : iCE40/yosys | |
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