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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-21 14:13:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | a323881e152c0d51728f3df773ac2f326544b379 (patch) | |
| tree | ef12adb4c3b88d682e15089680f92b134742ba5c /techlibs/ecp5/cells_sim.v | |
| parent | b3e2538a140cac36c32b133d4475a052cfc46809 (diff) | |
| download | yosys-a323881e152c0d51728f3df773ac2f326544b379.tar.gz yosys-a323881e152c0d51728f3df773ac2f326544b379.tar.bz2 yosys-a323881e152c0d51728f3df773ac2f326544b379.zip | |
xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 563592218..6f37823e4 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -186,6 +186,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- +(* abc9_box, lib_whitebox *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, @@ -222,10 +223,16 @@ module TRELLIS_DPR16X4 ( mem[WAD] <= DI; assign DO = mem[RAD]; + + specify + // TODO + (RAD *> DO) = 0; + endspecify endmodule // --------------------------------------- +(* abc9_box, lib_whitebox *) module DPR16X4C ( input [3:0] DI, input WCK, WRE, @@ -281,6 +288,10 @@ module DPR16X4C ( assign DO = ram[RAD]; + specify + // TODO + (RAD *> DO) = 0; + endspecify endmodule // --------------------------------------- @@ -295,7 +306,7 @@ endmodule // --------------------------------------- `ifdef YOSYS -(* abc9_flop=(SRMODE != "ASYNC"), lib_whitebox=(SRMODE != "ASYNC") *) +(* abc9_flop=(SRMODE != "ASYNC"), abc9_box=(SRMODE == "ASYNC"), lib_whitebox *) `endif module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); parameter GSR = "ENABLED"; @@ -351,15 +362,27 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); $setup(DI, negedge CLK, 0); $setup(CE, negedge CLK, 0); $setup(LSR, negedge CLK, 0); - if (muxlsr) (negedge CLK => (Q : DI)) = 0; - if (!muxlsr && muxce) (negedge CLK => (Q : srval)) = 0; +`ifndef YOSYS + if (muxlsr) (negedge CLK => (Q : srval)) = 0; +`else + if (muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif + if (!muxlsr && muxce) (negedge CLK => (Q : DI)) = 0; endspecify else specify $setup(DI, posedge CLK, 0); $setup(CE, posedge CLK, 0); $setup(LSR, posedge CLK, 0); +`ifndef YOSYS if (muxlsr) (posedge CLK => (Q : srval)) = 0; +`else + if (muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif if (!muxlsr && muxce) (posedge CLK => (Q : DI)) = 0; endspecify endgenerate |