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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 16:07:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 16:07:14 -0700 |
| commit | 9398921af1d21b47aa291d240a1f274418adcaf2 (patch) | |
| tree | c93649f494e78cb7745a0f64ce8a04443969cff2 /techlibs/ecp5/cells_sim.v | |
| parent | 550760cc721e8a617e5ca60b3dda70a223504765 (diff) | |
| download | yosys-9398921af1d21b47aa291d240a1f274418adcaf2.tar.gz yosys-9398921af1d21b47aa291d240a1f274418adcaf2.tar.bz2 yosys-9398921af1d21b47aa291d240a1f274418adcaf2.zip | |
Refactor for one "abc_carry" attribute on module
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 08ae0a112..98f915777 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -15,11 +15,9 @@ module L6MUX21 (input D0, D1, SD, output Z); endmodule // --------------------------------------- -(* abc_box_id=1, abc_carry, lib_whitebox *) -module CCU2C((* abc_carry_in *) input CIN, - input A0, B0, C0, D0, A1, B1, C1, D1, - output S0, S1, - (* abc_carry_out *) output COUT); +(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *) +module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, COUT); parameter [15:0] INIT0 = 16'h0000; parameter [15:0] INIT1 = 16'h0000; |