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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:59:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:59:03 -0700 |
| commit | 55acf3120fa47bb95be8a6551738f4f9b1c70a21 (patch) | |
| tree | 4f0fff0e6e2a85e53b33ef0c79e85b10cb3dd6a9 /techlibs/ecp5/cells_sim.v | |
| parent | 4cd1d21bfe412e9c6edb8aa74c19ee57370c56c4 (diff) | |
| download | yosys-55acf3120fa47bb95be8a6551738f4f9b1c70a21.tar.gz yosys-55acf3120fa47bb95be8a6551738f4f9b1c70a21.tar.bz2 yosys-55acf3120fa47bb95be8a6551738f4f9b1c70a21.zip | |
ecp5 to use abc_map.v and _unmap.v
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 2fcb0369e..f79a27312 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -107,11 +107,10 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -//(* abc_box_id=2 *) module TRELLIS_DPR16X4 ( - (* abc_scc_break *) input [3:0] DI, - (* abc_scc_break *) input [3:0] WAD, - (* abc_scc_break *) input WRE, + input [3:0] DI, + input [3:0] WAD, + input WRE, input WCK, input [3:0] RAD, output [3:0] DO |