iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	35	-709/+709
*	Added "trace" command	Clifford Wolf	2014-07-31	3	-2/+100
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	7	-9/+11
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	11	-15/+19
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31	3	-6/+6
*	Added "techmap -assert"	Clifford Wolf	2014-07-31	2	-14/+43
*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-10/+119
*	Added write_file command	Clifford Wolf	2014-07-30	2	-0/+77
*	Improvements in test_cell	Clifford Wolf	2014-07-30	1	-35/+89
*	Added "test_cell" command	Clifford Wolf	2014-07-29	2	-0/+185
*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	2	-0/+338
*	Allow "hierarchy -generate" for $__ cells	Clifford Wolf	2014-07-29	1	-1/+3
*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	2	-10/+19
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	2	-7/+11
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	25	-58/+42
*	Added techmap -extern	Clifford Wolf	2014-07-27	1	-16/+64
*	Added topological sorting to techmap	Clifford Wolf	2014-07-27	1	-20/+52
*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27	1	-2/+2
*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27	1	-1/+1
*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27	1	-29/+54
*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27	2	-13/+14
*	Added log_cmd_error_expection	Clifford Wolf	2014-07-27	1	-4/+1
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	10	-87/+85
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	57	-169/+169
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	46	-117/+117
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	33	-138/+138
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	6	-74/+29
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	15	-202/+96
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	3	-4/+4
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	6	-15/+15
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	31	-101/+147
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	45	-835/+835
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	45	-835/+835
*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26	2	-12/+5
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	30	-465/+171
*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25	1	-3/+3
*	Fixed memory corruption in "opt_reduce" pass	Clifford Wolf	2014-07-25	1	-5/+7
*	Disabled cover() for non-linux builds	Clifford Wolf	2014-07-25	1	-2/+5
*	Improvements in "cover" command	Clifford Wolf	2014-07-25	1	-11/+37
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	6	-46/+40
*	Added cover() calls to opt_const	Clifford Wolf	2014-07-24	1	-9/+45
*	Added "make SMALL=1"	Clifford Wolf	2014-07-24	1	-1/+4
*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	1	-6/+6
*	Added "cover" command	Clifford Wolf	2014-07-24	3	-1/+117
*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23	1	-4/+4
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	16	-48/+6
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	9	-211/+135
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	10	-86/+75
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	10	-24/+24
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	10	-24/+24