Using log_assert() instead of assert()

25 files changed, 42 insertions, 58 deletions

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 03fc9f937..d2be7dcf1 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -39,7 +39,6 @@
 #include "kernel/log.h"
 #include <unistd.h>
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 #include <dirent.h>
@@ -273,7 +272,7 @@ static void handle_loops()
 		// log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit));
 
 		for (int id2 : edges[id]) {
-			assert(in_edges_count[id2] > 0);
+			log_assert(in_edges_count[id2] > 0);
 			if (--in_edges_count[id2] == 0)
 				workpool.insert(id2);
 		}
@@ -331,7 +330,7 @@ static void handle_loops()
 			int id3 = map_signal(RTLIL::SigSpec(wire));
 			signal_list[id1].is_port = true;
 			signal_list[id3].is_port = true;
-			assert(id3 == int(in_edges_count.size()));
+			log_assert(id3 == int(in_edges_count.size()));
 			in_edges_count.push_back(0);
 			workpool.insert(id3);
 
@@ -778,7 +777,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 					for (auto &c : conn.second.chunks()) {
 						if (c.width == 0)
 							continue;
-						assert(c.width == 1);
+						log_assert(c.width == 1);
 						newsig.append(module->wires_[remap_name(c.wire->name)]);
 					}
 					cell->set(conn.first, newsig);
@@ -831,7 +830,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 
 		struct dirent **namelist;
 		int n = scandir(tempdir_name, &namelist, 0, alphasort);
-		assert(n >= 0);
+		log_assert(n >= 0);
 		for (int i = 0; i < n; i++) {
 			if (strcmp(namelist[i]->d_name, ".") && strcmp(namelist[i]->d_name, "..")) {
 				if (asprintf(&p, "%s/%s", tempdir_name, namelist[i]->d_name) < 0) log_abort();
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc
index 1fa1b4c9c..8c039e3e9 100644
--- a/passes/cmds/scc.cc
+++ b/passes/cmds/scc.cc
@@ -51,7 +51,7 @@ struct SccWorker
 
 	void run(RTLIL::Cell *cell, int depth, int maxDepth)
 	{
-		assert(workQueue.count(cell) > 0);
+		log_assert(workQueue.count(cell) > 0);
 
 		workQueue.erase(cell);
 		cellLabels[cell] = std::pair<int, int>(labelCounter, labelCounter);
@@ -166,7 +166,7 @@ struct SccWorker
 
 		while (workQueue.size() > 0) {
 			RTLIL::Cell *cell = *workQueue.begin();
-			assert(cellStack.size() == 0);
+			log_assert(cellStack.size() == 0);
 			cellDepth.clear();
 			run(cell, 0, maxDepth);
 		}
@@ -290,7 +290,7 @@ struct SccPass : public Pass {
 			}
 
 		if (selectMode) {
-			assert(origSelectPos >= 0);
+			log_assert(origSelectPos >= 0);
 			design->selection_stack[origSelectPos] = newSelection;
 			design->selection_stack[origSelectPos].optimize(design);
 		}
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 85c52277c..bbfa396ba 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1120,7 +1120,7 @@ struct SelectPass : public Pass {
 			work_stack.pop_back();
 		}
 
-		assert(design->selection_stack.size() > 0);
+		log_assert(design->selection_stack.size() > 0);
 
 		if (clear_mode) {
 			design->selection_stack.back() = RTLIL::Selection(true);
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 7ab1daf00..a2dd8051b 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -202,7 +202,7 @@ struct ShowWorker
 			for (int i = int(sig.chunks().size())-1; i >= 0; i--) {
 				const RTLIL::SigChunk &c = sig.chunks().at(i);
 				net = gen_signode_simple(c, false);
-				assert(!net.empty());
+				log_assert(!net.empty());
 				if (driver) {
 					label_string += stringf("<s%d> %d:%d - %d:%d |", i, pos, pos-c.width+1, c.offset+c.width-1, c.offset);
 					net_conn_map[net].in.insert(stringf("x%d:s%d", idx, i));
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index f107366d6..2da4794eb 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -157,9 +157,9 @@ struct FsmExpand
 			A.replace(input_sig, RTLIL::SigSpec(in_val));
 			B.replace(input_sig, RTLIL::SigSpec(in_val));
 			S.replace(input_sig, RTLIL::SigSpec(in_val));
-			assert(A.is_fully_const());
-			assert(B.is_fully_const());
-			assert(S.is_fully_const());
+			log_assert(A.is_fully_const());
+			log_assert(B.is_fully_const());
+			log_assert(S.is_fully_const());
 			truth_tab.push_back(ct.eval(cell, A.as_const(), B.as_const(), S.as_const()));
 		}
 
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 99352b10a..6da468321 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -109,7 +109,7 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d
 	RTLIL::SigSpec undef, constval;
 
 	if (ce.eval(ctrl_out, undef) && ce.eval(dff_in, undef)) {
-		assert(ctrl_out.is_fully_const() && dff_in.is_fully_const());
+		log_assert(ctrl_out.is_fully_const() && dff_in.is_fully_const());
 		FsmData::transition_t tr;
 		tr.state_in = state_in;
 		tr.state_out = states[ce.values_map(ce.assign_map(dff_in)).as_const()];
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 8aec25eba..c869ec729 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -98,7 +98,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 					generate_port_decl_t d = decl;
 					d.portname = portname;
 					d.index = *indices.begin();
-					assert(!indices.empty());
+					log_assert(!indices.empty());
 					indices.erase(d.index);
 					ports[d.index-1] = d;
 					portwidths[d.portname] = std::max(portwidths[d.portname], 1);
@@ -110,7 +110,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 			portnames.erase(portname);
 		}
 
-		assert(indices.empty());
+		log_assert(indices.empty());
 
 		RTLIL::Module *mod = new RTLIL::Module;
 		mod->name = celltype;
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index d32b5e1d3..84c6b9161 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -171,7 +171,7 @@ struct SubmodWorker
 			for (auto &conn : new_cell->connections_)
 				for (auto &bit : conn.second)
 					if (bit.wire != NULL) {
-						assert(wire_flags.count(bit.wire) > 0);
+						log_assert(wire_flags.count(bit.wire) > 0);
 						bit.wire = wire_flags[bit.wire].new_wire;
 					}
 			log("  cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index d2803ae78..40c68abc1 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -22,7 +22,6 @@
 #include <sstream>
 #include <algorithm>
 #include <stdlib.h>
-#include <assert.h>
 
 static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
 {
@@ -136,12 +135,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	mem->parameters["\\SIZE"] = RTLIL::Const(memory->size);
 	mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
 
-	assert(sig_wr_clk.size() == wr_ports);
-	assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
-	assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
-	assert(sig_wr_addr.size() == wr_ports * addr_bits);
-	assert(sig_wr_data.size() == wr_ports * memory->width);
-	assert(sig_wr_en.size() == wr_ports * memory->width);
+	log_assert(sig_wr_clk.size() == wr_ports);
+	log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
+	log_assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
+	log_assert(sig_wr_addr.size() == wr_ports * addr_bits);
+	log_assert(sig_wr_data.size() == wr_ports * memory->width);
+	log_assert(sig_wr_en.size() == wr_ports * memory->width);
 
 	mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
 	mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
@@ -152,11 +151,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	mem->set("\\WR_DATA", sig_wr_data);
 	mem->set("\\WR_EN", sig_wr_en);
 
-	assert(sig_rd_clk.size() == rd_ports);
-	assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
-	assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
-	assert(sig_rd_addr.size() == rd_ports * addr_bits);
-	assert(sig_rd_data.size() == rd_ports * memory->width);
+	log_assert(sig_rd_clk.size() == rd_ports);
+	log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
+	log_assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
+	log_assert(sig_rd_addr.size() == rd_ports * addr_bits);
+	log_assert(sig_rd_data.size() == rd_ports * memory->width);
 
 	mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
 	mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0);
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 85249142e..325056170 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -20,7 +20,6 @@
 #include "kernel/register.h"
 #include "kernel/log.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <sstream>
 
 static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 53394b19a..49291656c 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -22,7 +22,6 @@
 #include <sstream>
 #include <set>
 #include <stdlib.h>
-#include <assert.h>
 
 static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
 {
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index d2b9c0eeb..cdf7db04b 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -22,7 +22,6 @@
 #include <sstream>
 #include <algorithm>
 #include <stdlib.h>
-#include <assert.h>
 
 static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 {
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 6c20bddbb..4182c6f5d 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -23,7 +23,6 @@
 #include "kernel/log.h"
 #include "kernel/celltypes.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <set>
 
@@ -227,7 +226,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 			if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) {
 				maybe_del_wires.push_back(wire);
 			} else {
-				assert(SIZE(s1) == SIZE(s2));
+				log_assert(SIZE(s1) == SIZE(s2));
 				RTLIL::SigSig new_conn;
 				for (int i = 0; i < SIZE(s1); i++)
 					if (s1[i] != s2[i]) {
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 7578f1927..254fe5bb4 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -24,7 +24,6 @@
 #include "kernel/toposort.h"
 #include "kernel/log.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <algorithm>
 
@@ -495,7 +494,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			RTLIL::SigSpec new_a, new_b;
 
-			assert(SIZE(a) == SIZE(b));
+			log_assert(SIZE(a) == SIZE(b));
 			for (int i = 0; i < SIZE(a); i++) {
 				if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
 					cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type);
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 73baaf900..de12542dc 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -23,7 +23,6 @@
 #include "kernel/log.h"
 #include "kernel/celltypes.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <set>
 
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index b2b7cc8b9..8aadd1f23 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -24,7 +24,6 @@
 #include "kernel/celltypes.h"
 #include "libs/sha1/sha1.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <set>
 
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 45130229f..ad6e1a746 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -24,7 +24,6 @@
 #include "kernel/celltypes.h"
 #include "libs/sha1/sha1.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <set>
 
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index dc310bde0..91cafe3be 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -24,7 +24,6 @@
 #include <sstream>
 #include <stdlib.h>
 #include <stdio.h>
-#include <assert.h>
 
 static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
 {
@@ -288,7 +287,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 					inputs.append(it->signal);
 					compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0);
 				}
-				assert(inputs.size() == compare.size());
+				log_assert(inputs.size() == compare.size());
 
 				RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne");
 				cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1);
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index 99498505f..c72840c02 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -25,7 +25,7 @@
 
 static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule)
 {
-	assert(rule.compare.size() == 0);
+	log_assert(rule.compare.size() == 0);
 
 	while (1) {
 		RTLIL::SigSpec tmp = sig;
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index fb49182c2..e7661245e 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -23,7 +23,6 @@
 #include <sstream>
 #include <stdlib.h>
 #include <stdio.h>
-#include <assert.h>
 
 static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs)
 {
@@ -67,7 +66,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 		RTLIL::SigSpec sig = signal;
 
 		// get rid of don't-care bits
-		assert(sig.size() == comp.size());
+		log_assert(sig.size() == comp.size());
 		for (int i = 0; i < comp.size(); i++)
 			if (comp[i] == RTLIL::State::Sa) {
 				sig.remove(i);
@@ -125,7 +124,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
 static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw)
 {
-	assert(when_signal.size() == else_signal.size());
+	log_assert(when_signal.size() == else_signal.size());
 
 	std::stringstream sstr;
 	sstr << "$procmux$" << (RTLIL::autoidx++);
@@ -138,7 +137,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
 	if (ctrl_sig.size() == 0)
 		return when_signal;
-	assert(ctrl_sig.size() == 1);
+	log_assert(ctrl_sig.size() == 1);
 
 	// prepare multiplexer output signal
 	RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size());
@@ -159,11 +158,11 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
 static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)
 {
-	assert(last_mux_cell != NULL);
-	assert(when_signal.size() == last_mux_cell->get("\\A").size());
+	log_assert(last_mux_cell != NULL);
+	log_assert(when_signal.size() == last_mux_cell->get("\\A").size());
 
 	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
-	assert(ctrl_sig.size() == 1);
+	log_assert(ctrl_sig.size() == 1);
 	last_mux_cell->type = "$pmux";
 
 	RTLIL::SigSpec new_s = last_mux_cell->get("\\S");
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc
index 9e5f413a2..61844d5eb 100644
--- a/passes/proc/proc_rmdead.cc
+++ b/passes/proc/proc_rmdead.cc
@@ -23,7 +23,6 @@
 #include <sstream>
 #include <stdlib.h>
 #include <stdio.h>
-#include <assert.h>
 #include <set>
 
 static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index dce312065..430628e46 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -335,7 +335,7 @@ struct SatHelper
 
 	int setup_proof(int timestep = -1)
 	{
-		assert(prove.size() || prove_x.size() || prove_asserts);
+		log_assert(prove.size() || prove_x.size() || prove_asserts);
 
 		RTLIL::SigSpec big_lhs, big_rhs;
 		std::vector<int> prove_bits;
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 8587f53b0..9c5fa7f71 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -23,7 +23,6 @@
 #include "libs/subcircuit/subcircuit.h"
 #include <algorithm>
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 
@@ -100,7 +99,7 @@ namespace
 			RTLIL::Cell *haystackCell = (RTLIL::Cell*) haystackUserData;
 
 			if (!needleCell || !haystackCell) {
-				assert(!needleCell && !haystackCell);
+				log_assert(!needleCell && !haystackCell);
 				return true;
 			}
 
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index b327ba832..5c3e4c68f 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -21,7 +21,6 @@
 #include "kernel/sigtools.h"
 #include "kernel/log.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 79e70a59c..5a69baca5 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -23,7 +23,6 @@
 #include "kernel/toposort.h"
 #include "kernel/log.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 
@@ -47,7 +46,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
 		if (chunk.wire != NULL) {
 			std::string wire_name = chunk.wire->name;
 			apply_prefix(prefix, wire_name);
-			assert(module->wires_.count(wire_name) > 0);
+			log_assert(module->wires_.count(wire_name) > 0);
 			chunk.wire = module->wires_[wire_name];
 		}
 	sig = chunks;
@@ -167,7 +166,7 @@ struct TechmapWorker
 				c.second.remove(c.first.size(), c.second.size() - c.first.size());
 			if (c.second.size() < c.first.size())
 				c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
-			assert(c.first.size() == c.second.size());
+			log_assert(c.first.size() == c.second.size());
 			if (flatten_mode) {
 				// more conservative approach:
 				// connect internal and external wires
@@ -427,7 +426,7 @@ struct TechmapWorker
 							const char *q = strrchr(p+1, '.');
 							q = q ? q : p+1;
 
-							assert(!strncmp(q, "_TECHMAP_DO_", 12));
+							log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
 							std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
 							while (tpl->wires_.count(new_name))
 								new_name += "_";