Changed more code to the new RTLIL::Wire constructors

6 files changed, 29 insertions, 74 deletions

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 519dce452..721d5c987 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -31,21 +31,15 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 
 	for (auto &it : module->wires)
 		if (it.first == from_name) {
-			RTLIL::Wire *wire = it.second;
-			log("Renaming wire %s to %s in module %s.\n", wire->name.c_str(), to_name.c_str(), module->name.c_str());
-			module->wires.erase(wire->name);
-			wire->name = to_name;
-			module->add(wire);
+			log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
+			module->rename(it.second, to_name);
 			return;
 		}
 
 	for (auto &it : module->cells)
 		if (it.first == from_name) {
-			RTLIL::Cell *cell = it.second;
-			log("Renaming cell %s to %s in module %s.\n", cell->name.c_str(), to_name.c_str(), module->name.c_str());
-			module->cells.erase(cell->name);
-			cell->name = to_name;
-			module->add(cell);
+			log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
+			module->rename(it.second, to_name);
 			return;
 		}
 
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 8b7e04062..61de44066 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -224,14 +224,14 @@ struct SpliceWorker
 
 		for (auto &it : rework_wires)
 		{
-			module->wires.erase(it.first->name);
-			RTLIL::Wire *new_port = new RTLIL::Wire(*it.first);
-			it.first->name = NEW_ID;
+			std::string orig_name = it.first->name;
+			module->rename(it.first, NEW_ID);
+
+			RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
 			it.first->port_id = 0;
 			it.first->port_input = false;
 			it.first->port_output = false;
-			module->add(it.first);
-			module->add(new_port);
+
 			module->connect(RTLIL::SigSig(new_port, it.second));
 		}
 	}
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 9ce3b43d3..21af63a36 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -208,11 +208,11 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 	}
 }
 
-static void add_new_wire(RTLIL::Module *module, RTLIL::Wire *wire)
+static RTLIL::Wire *add_new_wire(RTLIL::Module *module, std::string name, int width = 1)
 {
-	if (module->count_id(wire->name))
-		log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", RTLIL::id2cstr(wire->name));
-	module->add(wire);
+	if (module->count_id(name))
+		log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name));
+	return module->addWire(name, width);
 }
 
 struct ExposePass : public Pass {
@@ -448,7 +448,6 @@ struct ExposePass : public Pass {
 			SigMap sigmap(module);
 
 			SigMap out_to_in_map;
-			std::vector<RTLIL::Wire*> new_wires;
 
 			for (auto &it : module->wires)
 			{
@@ -468,20 +467,14 @@ struct ExposePass : public Pass {
 				}
 
 				if (flag_cut) {
-					RTLIL::Wire *in_wire = new RTLIL::Wire;
-					in_wire->name = it.second->name + sep + "i";
-					in_wire->width = it.second->width;
+					RTLIL::Wire *in_wire = add_new_wire(module, it.second->name + sep + "i", it.second->width);
 					in_wire->port_input = true;
 					out_to_in_map.add(sigmap(it.second), in_wire);
-					new_wires.push_back(in_wire);
 				}
 			}
 
 			if (flag_cut)
 			{
-				for (auto it : new_wires)
-					add_new_wire(module, it);
-
 				for (auto &it : module->cells) {
 					if (!ct.cell_known(it.second->type))
 						continue;
@@ -507,10 +500,7 @@ struct ExposePass : public Pass {
 
 				dff_map_info_t &info = dq.second;
 
-				RTLIL::Wire *wire_dummy_q = new RTLIL::Wire;
-				wire_dummy_q->name = NEW_ID;
-				wire_dummy_q->width = 0;
-				add_new_wire(module, wire_dummy_q);
+				RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
 
 				for (auto &cell_name : info.cells) {
 					RTLIL::Cell *cell = module->cells.at(cell_name);
@@ -521,12 +511,9 @@ struct ExposePass : public Pass {
 					cell->set("\\Q", cell_q_bits);
 				}
 
-				RTLIL::Wire *wire_q = new RTLIL::Wire;
-				wire_q->name = wire->name + sep + "q";
-				wire_q->width = wire->width;
+				RTLIL::Wire *wire_q = add_new_wire(module, wire->name + sep + "q", wire->width);
 				wire_q->port_input = true;
 				log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name));
-				add_new_wire(module, wire_q);
 
 				RTLIL::SigSig connect_q;
 				for (size_t i = 0; i < wire_bits_vec.size(); i++) {
@@ -538,19 +525,14 @@ struct ExposePass : public Pass {
 				}
 				module->connect(connect_q);
 
-				RTLIL::Wire *wire_d = new RTLIL::Wire;
-				wire_d->name = wire->name + sep + "d";
-				wire_d->width = wire->width;
+				RTLIL::Wire *wire_d = add_new_wire(module, wire->name + sep + "d", wire->width);
 				wire_d->port_output = true;
 				log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name));
-				add_new_wire(module, wire_d);
 				module->connect(RTLIL::SigSig(wire_d, info.sig_d));
 
-				RTLIL::Wire *wire_c = new RTLIL::Wire;
-				wire_c->name = wire->name + sep + "c";
+				RTLIL::Wire *wire_c = add_new_wire(module, wire->name + sep + "c");
 				wire_c->port_output = true;
 				log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name));
-				add_new_wire(module, wire_c);
 				if (info.clk_polarity) {
 					module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
 				} else {
@@ -564,11 +546,9 @@ struct ExposePass : public Pass {
 
 				if (info.sig_arst != RTLIL::State::Sm)
 				{
-					RTLIL::Wire *wire_r = new RTLIL::Wire;
-					wire_r->name = wire->name + sep + "r";
+					RTLIL::Wire *wire_r = add_new_wire(module, wire->name + sep + "r");
 					wire_r->port_output = true;
 					log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name));
-					add_new_wire(module, wire_r);
 					if (info.arst_polarity) {
 						module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
 					} else {
@@ -580,12 +560,9 @@ struct ExposePass : public Pass {
 						c->set("\\Y", wire_r);
 					}
 
-					RTLIL::Wire *wire_v = new RTLIL::Wire;
-					wire_v->name = wire->name + sep + "v";
-					wire_v->width = wire->width;
+					RTLIL::Wire *wire_v = add_new_wire(module, wire->name + sep + "v", wire->width);
 					wire_v->port_output = true;
 					log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name));
-					add_new_wire(module, wire_v);
 					module->connect(RTLIL::SigSig(wire_v, info.arst_value));
 				}
 			}
@@ -616,14 +593,11 @@ struct ExposePass : public Pass {
 							if (!p->port_input && !p->port_output)
 								continue;
 
-							RTLIL::Wire *w = new RTLIL::Wire;
-							w->name = cell->name + sep + RTLIL::unescape_id(p->name);
-							w->width = p->width;
+							RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(p->name), p->width);
 							if (p->port_input)
 								w->port_output = true;
 							if (p->port_output)
 								w->port_input = true;
-							add_new_wire(module, w);
 
 							log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
@@ -641,14 +615,11 @@ struct ExposePass : public Pass {
 					{
 						for (auto &it : cell->connections())
 						{
-							RTLIL::Wire *w = new RTLIL::Wire;
-							w->name = cell->name + sep + RTLIL::unescape_id(it.first);
-							w->width = it.second.size();
+							RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(it.first), it.second.size());
 							if (ct.cell_input(cell->type, it.first))
 								w->port_output = true;
 							if (ct.cell_output(cell->type, it.first))
 								w->port_input = true;
-							add_new_wire(module, w);
 
 							log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index b8c349f5c..92bcafc00 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -729,13 +729,10 @@ struct ExtractPass : public Pass {
 
 				int portCounter = 1;
 				for (auto wire : wires) {
-					RTLIL::Wire *newWire = new RTLIL::Wire;
-					newWire->name = wire->name;
-					newWire->width = wire->width;
+					RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width);
 					newWire->port_id = portCounter++;
 					newWire->port_input = true;
 					newWire->port_output = true;
-					newMod->add(newWire);
 				}
 
 				for (auto cell : cells) {
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 114d28e25..ab3bb3ed0 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -164,13 +164,8 @@ struct IopadmapPass : public Pass {
 				log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
 
 				RTLIL::Wire *new_wire = NULL;
-				if (!portname2.empty()) {
-					new_wire = new RTLIL::Wire;
-					*new_wire = *wire;
-					wire->name = NEW_ID;
-					module->wires[wire->name] = wire;
-					module->wires[new_wire->name] = new_wire;
-				}
+				if (!portname2.empty())
+					new_wire = module->addWire(NEW_ID, wire);
 
 				if (flag_bits)
 				{
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 9dcd6a45b..bee1df406 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -128,14 +128,14 @@ struct TechmapWorker
 		for (auto &it : tpl->wires) {
 			if (it.second->port_id > 0)
 				positional_ports[stringf("$%d", it.second->port_id)] = it.first;
-			RTLIL::Wire *w = new RTLIL::Wire(*it.second);
-			apply_prefix(cell->name, w->name);
+			std::string w_name = it.second->name;
+			apply_prefix(cell->name, w_name);
+			RTLIL::Wire *w = module->addWire(w_name, it.second);
 			w->port_input = false;
 			w->port_output = false;
 			w->port_id = 0;
 			if (it.second->get_bool_attribute("\\_techmap_special_"))
 				w->attributes.clear();
-			module->add(w);
 			design->select(module, w);
 		}
 
@@ -381,7 +381,6 @@ struct TechmapWorker
 								log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
 
 							techmap_wire_names.erase(it.first);
-							tpl->wires.erase(data.wire->name);
 
 							const char *p = data.wire->name.c_str();
 							const char *q = strrchr(p+1, '.');
@@ -391,8 +390,7 @@ struct TechmapWorker
 							std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
 							while (tpl->wires.count(new_name))
 								new_name += "_";
-							data.wire->name = new_name;
-							tpl->add(data.wire);
+							tpl->rename(data.wire, new_name);
 
 							std::string cmd_string = data.value.as_const().decode_string();
 							Pass::call_on_module(map, tpl, cmd_string);