Added copy-constructor-like module->addCell(name, other) method

2 files changed, 5 insertions, 12 deletions

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 204f899a0..be580ca04 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -162,10 +162,7 @@ struct SubmodWorker
 		}
 
 		for (RTLIL::Cell *cell : submod.cells) {
-			RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell->type);
-			new_cell->connections = cell->connections;
-			new_cell->parameters = cell->parameters;
-			new_cell->attributes = cell->attributes;
+			RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
 			for (auto &conn : new_cell->connections)
 				for (auto &bit : conn.second)
 					if (bit.wire != NULL) {
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index e8385844d..94cb1e8dd 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -183,22 +183,18 @@ struct TechmapWorker
 		for (auto &it : tpl->cells)
 		{
 			RTLIL::IdString c_name = it.second->name;
-			RTLIL::IdString c_type = it.second->type;
-
-			if (!flatten_mode && c_type.substr(0, 2) == "\\$")
-				c_type = c_type.substr(1);
 
 			if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_")
 				c_name = orig_cell_name;
 			else
 				apply_prefix(cell->name, c_name);
 
-			RTLIL::Cell *c = module->addCell(c_name, c_type);
-			c->connections = it.second->connections;
-			c->parameters = it.second->parameters;
-			c->attributes = it.second->attributes;
+			RTLIL::Cell *c = module->addCell(c_name, it.second);
 			design->select(module, c);
 
+			if (!flatten_mode && c->type.substr(0, 2) == "\\$")
+				c->type = c->type.substr(1);
+
 			for (auto &it2 : c->connections) {
 				apply_prefix(cell->name, it2.second, module);
 				port_signal_map.apply(it2.second);