iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
...
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	14	-38/+38
\|
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	11	-35/+35
\|
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-15/+9
\|
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	4	-58/+25
\|
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-1/+1
\|
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	6	-10/+10
\|
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	10	-33/+33
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	10	-33/+33
\|
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	2	-13/+6
\|
*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25	1	-3/+3
\|
*	Disabled cover() for non-linux builds	Clifford Wolf	2014-07-25	1	-2/+5
\|
*	Improvements in "cover" command	Clifford Wolf	2014-07-25	1	-11/+37
\|
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-2/+2
\|
*	Added "cover" command	Clifford Wolf	2014-07-24	3	-1/+117
\|
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	4	-7/+1
\|
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	3	-36/+34
\|
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	4	-5/+5
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	10	-39/+39
\|
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	10	-39/+39
\|
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	3	-4/+4
\|
*	Added "select -assert-count"	Clifford Wolf	2014-07-20	1	-6/+43
\|
*	Improved seeding of color rng in show command	Clifford Wolf	2014-07-18	1	-1/+3
\|
*	Added %D and %c select commands	Clifford Wolf	2014-06-14	1	-2/+20
\|
*	added tee cmd	Clifford Wolf	2014-06-03	2	-0/+89
\|
*	fixed syntax error in dot file created by "show" command	Clifford Wolf	2014-05-10	1	-1/+1
\|
*	- kernel/register.h, kernel/driver.cc: refactor ↵	Siesh1oo	2014-03-12	1	-1/+2
\| \| \| \| \| \| \|	rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	1	-0/+1
\| \| \| \|	(see https://github.com/cliffordwolf/yosys/pull/28)
*	Added "design -push" and "design -pop"	Clifford Wolf	2014-02-20	1	-8/+45
\|
*	Added connwrappers command	Clifford Wolf	2014-02-20	2	-0/+206
\|
*	Fixed use of selection in splitnets command	Clifford Wolf	2014-02-16	1	-1/+1
\|
*	Added != support for relational select pattern	Clifford Wolf	2014-02-16	1	-1/+7
\|
*	Added delete {-input\|-output\|-port}	Clifford Wolf	2014-02-09	1	-5/+36
\|
*	Bugfix in delete command	Clifford Wolf	2014-02-09	1	-1/+3
\|
*	Build fixes for log cmd	Clifford Wolf	2014-02-08	1	-2/+2
\|
*	added "log" command	Johann Glaser	2014-02-08	2	-0/+79
\|
*	Added various new options to splice command	Clifford Wolf	2014-02-08	1	-5/+105
\|
*	Added %a select operator	Clifford Wolf	2014-02-08	1	-0/+32
\|
*	Moved some passes to other source directories	Clifford Wolf	2014-02-08	2	-0/+300
\|
*	Now also move net labes to the right position in splice cmd	Clifford Wolf	2014-02-08	1	-3/+10
\|
*	Added splice command	Clifford Wolf	2014-02-07	2	-0/+253
\|
*	Added log_header() to splitnets	Clifford Wolf	2014-02-07	1	-0/+2
\|
*	Fixed use of "cmd_error" in passes/cmds/design.cc	Clifford Wolf	2014-02-07	1	-2/+2
\|
*	Added copy command	Clifford Wolf	2014-02-06	2	-0/+55
\|
*	Added design -stash/-copy-from/-copy-to	Clifford Wolf	2014-02-06	1	-13/+99
\|
*	Added support for s: select expressions (wire width)	Clifford Wolf	2014-02-06	1	-1/+21
\|
*	Added i:, o:, and x: selection pattern	Clifford Wolf	2014-02-06	1	-0/+18
\|
*	Added support for %m selection op	Clifford Wolf	2014-02-06	1	-0/+16
\|
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-06	1	-0/+25
\|\
\| *	new %s: add sub-modules to selection	Johann Glaser	2014-02-06	1	-0/+25
\| \|
* \|	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	Clifford Wolf	2014-02-06	1	-3/+3
\|/