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* abc/blifparse files reorganizationClifford Wolf2015-05-174-1840/+0
* Added .barbuf support to abc BLIF parserClifford Wolf2015-05-131-0/+20
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-051-0/+88
* Fixed detection of absolute paths in ABC for win32Clifford Wolf2015-03-221-3/+3
* Fixed typos found by lintianRuben Undheim2015-02-011-1/+1
* Added "abc -lut w1:w2"Clifford Wolf2015-01-151-5/+21
* Fixed typo in ABC commandClifford Wolf2014-12-301-2/+2
* Less verbose ABC outputClifford Wolf2014-12-292-21/+55
* Improved ABC clock domain partitioningClifford Wolf2014-12-231-2/+59
* Added "abc -markgroups"Clifford Wolf2014-12-231-0/+20
* Added support for multiple clock domains to "abc" passClifford Wolf2014-12-211-64/+123
* Fixed "abc" pass for clk and enable signals driven by logicClifford Wolf2014-12-211-6/+8
* Added DFFE support to "abc" passClifford Wolf2014-12-201-11/+78
* Also look for yosys-abc in parent dir on win32Clifford Wolf2014-10-181-0/+5
* Header changes so it will compile on VSWilliam Speirs2014-10-171-2/+5
* More win32/abc fixesClifford Wolf2014-10-121-38/+33
* Added make_temp_{file,dir}() and remove_directory() APIsClifford Wolf2014-10-121-31/+15
* Using stringf() instead of asprintf() in "abc" passClifford Wolf2014-10-121-29/+24
* Added run_command() api to replace system() and popen()Clifford Wolf2014-10-121-73/+70
* Added API for generic cell cost calculationsClifford Wolf2014-10-091-15/+16
* Added $_BUF_ cell typeClifford Wolf2014-10-031-3/+7
* namespace YosysClifford Wolf2014-09-273-5/+13
* Small improvements in "abc" command handle_loops() functionClifford Wolf2014-09-191-6/+9
* Using "NOT" instead of "INV" as cell name in default abc genlib fileClifford Wolf2014-09-191-2/+2
* Do not run "scorr" in "abc -fast"Clifford Wolf2014-09-181-4/+4
* Added "abc -fast"Clifford Wolf2014-09-181-6/+31
* Fixed $_NOR vs. $_NOR_ typo in abc.ccClifford Wolf2014-09-161-1/+1
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-25/+161
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-151-2/+2
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-2/+2
* Added module->portsClifford Wolf2014-08-141-2/+1
* Added "abc -D" for setting delay targetClifford Wolf2014-08-141-5/+18
* Filter ANSI escape sequences from ABC outputClifford Wolf2014-08-131-0/+15
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-1/+1
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-021-1/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-312-37/+37
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-1/+1
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-2/+2
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-5/+4
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-272-3/+3
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-6/+6
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-272-34/+34
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-262-22/+8
* Manual fixes for new cell connections APIClifford Wolf2014-07-262-2/+2
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-262-48/+48
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-262-48/+48
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-252-50/+16
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-19/+19
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-3/+0
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-30/+23