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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-16 12:45:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-16 12:45:05 +0200 |
| commit | 9ae559b9909a5042cb60b44b020d87b3d5b60b8b (patch) | |
| tree | b29939e631233e9f0543ee28172ddfcfff6cc1ae /passes/abc | |
| parent | ae02d9cb9a990bfbe76d056fd341d88a9a5f129c (diff) | |
| download | yosys-9ae559b9909a5042cb60b44b020d87b3d5b60b8b.tar.gz yosys-9ae559b9909a5042cb60b44b020d87b3d5b60b8b.tar.bz2 yosys-9ae559b9909a5042cb60b44b020d87b3d5b60b8b.zip | |
Fixed $_NOR vs. $_NOR_ typo in abc.cc
Diffstat (limited to 'passes/abc')
| -rw-r--r-- | passes/abc/abc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index fd56668cf..b18f88352 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -166,7 +166,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) return; } - if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR", "$_XOR_", "$_XNOR_")) + if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_")) { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_b = cell->getPort("\\B"); |