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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:18:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:18:40 +0200 |
| commit | b64b38eea2e9a7de30d6045f069c86bf4446134f (patch) | |
| tree | 1792429b244f7af0b4ed33f8e57c1e591c8efd02 /passes/abc | |
| parent | f092b5014895dc5dc62b8103fcedf94cfa9f85a8 (diff) | |
| download | yosys-b64b38eea2e9a7de30d6045f069c86bf4446134f.tar.gz yosys-b64b38eea2e9a7de30d6045f069c86bf4446134f.tar.bz2 yosys-b64b38eea2e9a7de30d6045f069c86bf4446134f.zip | |
Renamed $lut ports to follow A-Y naming scheme
Diffstat (limited to 'passes/abc')
| -rw-r--r-- | passes/abc/blifparse.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index bc8f343a5..1fbb5720d 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -195,8 +195,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut"); cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); - cell->setPort("\\I", input_sig); - cell->setPort("\\O", output_sig); + cell->setPort("\\A", input_sig); + cell->setPort("\\Y", output_sig); lutptr = &cell->parameters.at("\\LUT"); lut_default_state = RTLIL::State::Sx; continue; |