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author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 13:19:47 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 13:19:47 +0200 |
commit | 1cb25c05b37b0172dbc50e140fe20f25d973dd8a (patch) | |
tree | 4bccb9f45ccad05346697c79afca9a1b21dced9c /passes/abc | |
parent | 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 (diff) | |
download | yosys-1cb25c05b37b0172dbc50e140fe20f25d973dd8a.tar.gz yosys-1cb25c05b37b0172dbc50e140fe20f25d973dd8a.tar.bz2 yosys-1cb25c05b37b0172dbc50e140fe20f25d973dd8a.zip |
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Diffstat (limited to 'passes/abc')
-rw-r--r-- | passes/abc/abc.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index d2be7dcf1..d204e93c6 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -313,7 +313,7 @@ static void handle_loops() } std::stringstream sstr; - sstr << "$abcloop$" << (RTLIL::autoidx++); + sstr << "$abcloop$" << (autoidx++); RTLIL::Wire *wire = module->addWire(sstr.str()); bool first_line = true; @@ -400,7 +400,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str, bool keepff) { module = current_module; - map_autoidx = RTLIL::autoidx++; + map_autoidx = autoidx++; signal_map.clear(); signal_list.clear(); |