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* Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970Clifford Wolf2019-04-301-1/+1
* Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-221-1/+97
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| * Global lists in rtlil.cc are now static objectsBenedikt Tutzer2019-04-031-10/+10
| * Merge remote-tracking branch 'origin/master' into feature/python_bindingsBenedikt Tutzer2019-03-281-3/+31
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| * | added some checks if python is enabled to make sure everything compiles if py...Benedikt Tutzer2018-08-201-4/+2
| * | Added Wrappers for:Benedikt Tutzer2018-08-131-1/+31
| * | added destructors for wires and cellsBenedikt Tutzer2018-07-101-0/+14
| * | removed debug outputBenedikt Tutzer2018-07-091-1/+0
| * | multiple designs can now exist independent from each other. Cells/Wires/Modul...Benedikt Tutzer2018-07-091-0/+55
* | | Add "wbflip" commandClifford Wolf2019-04-201-2/+5
* | | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-3/+3
* | | Add "read_ilang -lib"Clifford Wolf2019-04-051-0/+24
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* | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signalsClifford Wolf2019-03-231-1/+1
* | Add fmcombine passClifford Wolf2019-03-151-2/+2
* | Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-111-0/+2
* | Add FF support to wreduceClifford Wolf2019-02-201-0/+3
* | proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-231-0/+10
* | Documentation improvements etc.Ruben Undheim2018-10-131-3/+1
* | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+1
* | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+15
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* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+21
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-051-1/+3
* Add RTLIL::Const::is_fully_ones()Clifford Wolf2017-12-141-0/+11
* Add SigSpec::is_fully_ones()Clifford Wolf2017-12-141-0/+15
* Add src arguments to all cell creator helper functionsClifford Wolf2017-09-091-56/+91
* Update more stuff to use get_src_attribute() and set_src_attribute()Clifford Wolf2017-09-011-1/+1
* Merge remote-tracking branch 'upstream/master'Jason Lowdermilk2017-08-301-0/+16
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| * Add {get,set}_src_attribute() methods on RTLIL::AttrObjectClifford Wolf2017-08-301-0/+16
* | fix indent levelJason Lowdermilk2017-08-301-2/+2
* | Add support for source line tracking through synthesis phaseJason Lowdermilk2017-08-291-3/+4
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* Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()Clifford Wolf2017-08-181-0/+33
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-26/+30
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-1/+17
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-1/+9
* Fix RTLIL::Memory::start_offset initializationClifford Wolf2017-01-251-0/+1
* Bugfix in RTLIL::SigSpec::remove2()Clifford Wolf2016-12-311-3/+4
* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-151-0/+2
* Added $anyseq cell typeClifford Wolf2016-10-141-1/+10
* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-0/+25
* Improvements in assertpmuxClifford Wolf2016-09-071-0/+16
* Removed $aconst cell typeClifford Wolf2016-08-301-1/+1
* Removed $predict againClifford Wolf2016-08-281-9/+1
* Fixed handling of transparent bram rd ports on ROMsClifford Wolf2016-08-271-0/+1
* Added $anyconst and $aconstClifford Wolf2016-07-271-0/+6
* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-0/+6
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-2/+2
* Added basic support for $expect cellsClifford Wolf2016-07-131-8/+17
* A few modifications after pull request commentsRuben Undheim2016-06-181-1/+1
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-181-0/+2
* Improved support for $sop cellsClifford Wolf2016-06-171-1/+1
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