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author | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2019-04-03 14:27:39 +0200 |
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committer | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2019-04-03 14:27:39 +0200 |
commit | 827a96d3a38afe025c9efbd182069a9c9adee267 (patch) | |
tree | e2f99a1e4c4b509e31c572ad34c0c4a2f95e39c2 /kernel/rtlil.cc | |
parent | fd7fb1377d4d30d692c78eb55173198339fea17d (diff) | |
download | yosys-827a96d3a38afe025c9efbd182069a9c9adee267.tar.gz yosys-827a96d3a38afe025c9efbd182069a9c9adee267.tar.bz2 yosys-827a96d3a38afe025c9efbd182069a9c9adee267.zip |
Global lists in rtlil.cc are now static objects
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index efe2c3559..bb870f66f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -387,10 +387,10 @@ RTLIL::Design::~Design() } #ifdef WITH_PYTHON -static std::map<unsigned int, RTLIL::Design*> *all_designs = new std::map<unsigned int, RTLIL::Design*>(); +static std::map<unsigned int, RTLIL::Design*> all_designs; std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void) { - return all_designs; + return &all_designs; } #endif @@ -671,10 +671,10 @@ RTLIL::Module::~Module() } #ifdef WITH_PYTHON -static std::map<unsigned int, RTLIL::Module*> *all_modules = new std::map<unsigned int, RTLIL::Module*>(); +static std::map<unsigned int, RTLIL::Module*> all_modules; std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void) { - return all_modules; + return &all_modules; } #endif @@ -2253,10 +2253,10 @@ RTLIL::Wire::~Wire() } #ifdef WITH_PYTHON -static std::map<unsigned int, RTLIL::Wire*> *all_wires = new std::map<unsigned int, RTLIL::Wire*>(); +static std::map<unsigned int, RTLIL::Wire*> all_wires; std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void) { - return all_wires; + return &all_wires; } #endif @@ -2296,10 +2296,10 @@ RTLIL::Cell::~Cell() } #ifdef WITH_PYTHON -static std::map<unsigned int, RTLIL::Cell*> *all_cells = new std::map<unsigned int, RTLIL::Cell*>(); +static std::map<unsigned int, RTLIL::Cell*> all_cells; std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void) { - return all_cells; + return &all_cells; } #endif @@ -3959,10 +3959,10 @@ RTLIL::Memory::~Memory() { RTLIL::Memory::get_all_memorys()->erase(hashidx_); } -static std::map<unsigned int, RTLIL::Memory*> *all_memorys = new std::map<unsigned int, RTLIL::Memory*>(); +static std::map<unsigned int, RTLIL::Memory*> all_memorys; std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void) { - return all_memorys; + return &all_memorys; } #endif YOSYS_NAMESPACE_END |