| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge pull request #1845 from YosysHQ/eddie/kernel_speedup | Eddie Hung | 2020-04-02 | 1 | -288/+244 |
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| | * | kernel: pass-by-value into Design::scratchpad_set_string() too | Eddie Hung | 2020-03-27 | 1 | -2/+2 |
| | * | kernel: Cell::set{Port,Param}() to pass by value, but use std::move | Eddie Hung | 2020-03-26 | 1 | -5/+5 |
| | * | kernel: SigSpec copies to not trigger pack() | Eddie Hung | 2020-03-18 | 1 | -33/+4 |
| | * | kernel: more pass by const ref, more speedups | Eddie Hung | 2020-03-18 | 1 | -180/+174 |
| | * | kernel: speedup | Eddie Hung | 2020-03-18 | 1 | -30/+23 |
| | * | kernel: fix DeleteWireWorker | Eddie Hung | 2020-03-17 | 1 | -9/+4 |
| | * | kernel: SigSpec use more const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-13 | 1 | -31/+39 |
| | * | kernel: optimise Module::remove(const pool<RTLIL::Wire*>() | Eddie Hung | 2020-03-12 | 1 | -10/+5 |
| * | | Add support for SystemVerilog-style `define to Verilog frontend | Rupert Swarbrick | 2020-03-27 | 1 | -0/+2 |
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| * | Closes #1717. Add more precise Verilog source location information to AST and... | Alberto Gonzalez | 2020-02-23 | 1 | -2/+0 |
| * | specify: system timing checks to accept min:typ:max triple | Eddie Hung | 2020-02-13 | 1 | -2/+6 |
| * | Add RTLIL::constpad, init by yosys_setup(); use for abc9 | Eddie Hung | 2020-01-08 | 1 | -0/+1 |
| * | Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs | Clifford Wolf | 2020-01-02 | 1 | -4/+25 |
| * | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. | whitequark | 2019-12-04 | 1 | -3/+21 |
| * | Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again | Eddie Hung | 2019-10-04 | 1 | -0/+6 |
| * | Fix typo | Eddie Hung | 2019-09-30 | 1 | -1/+1 |
| * | Avoid work in replace() if rules empty. | Henner Zeller | 2019-09-29 | 1 | -0/+2 |
| * | Use more ID::{A,B,Y,blackbox,whitebox} | Eddie Hung | 2019-08-15 | 1 | -96/+96 |
| * | Add YOSYS_NO_IDS_REFCNT configuration macro | Clifford Wolf | 2019-08-11 | 1 | -1/+3 |
| * | Use ID() in kernel/*, add simple ID:: hack (to be improved upon later) | Clifford Wolf | 2019-08-11 | 1 | -578/+585 |
| * | More improvements and cleanups in IdString subsystem | Clifford Wolf | 2019-08-11 | 1 | -0/+2 |
| * | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -6/+6 |
| * | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -3/+3 |
| * | Fix typos | Eddie Hung | 2019-08-06 | 1 | -2/+2 |
| * | Use std::stoi instead of atoi(<str>.c_str()) | Eddie Hung | 2019-08-06 | 1 | -3/+3 |
| * | Use IdString::begins_with() | Eddie Hung | 2019-08-06 | 1 | -4/+4 |
| * | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
| * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -0/+2 |
| * | In RTLIL::Module::check(), check process invariants. | whitequark | 2019-06-19 | 1 | -1/+28 |
| * | Add rewrite_sigspecs2, Improve remove() wires | Clifford Wolf | 2019-05-15 | 1 | -7/+22 |
| * | Minor optimization to get_attribute_bool | Matthew Daiter | 2019-05-07 | 1 | -4/+8 |
| * | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 1 | -1/+1 |
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| | * | Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970 | Clifford Wolf | 2019-04-30 | 1 | -1/+1 |
| * | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| * | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -1/+2 |
| * | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -0/+15 |
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| * | | Add InternalCellChecker support for $specify2 and $specify3 | Clifford Wolf | 2019-04-23 | 1 | -7/+21 |
| * | | Add specify parser | Clifford Wolf | 2019-04-23 | 1 | -0/+10 |
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| * | Merge pull request #905 from christian-krieg/feature/python_bindings | Clifford Wolf | 2019-04-22 | 1 | -1/+97 |
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| | * | Global lists in rtlil.cc are now static objects | Benedikt Tutzer | 2019-04-03 | 1 | -10/+10 |
| | * | Merge remote-tracking branch 'origin/master' into feature/python_bindings | Benedikt Tutzer | 2019-03-28 | 1 | -3/+31 |
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| | * | | added some checks if python is enabled to make sure everything compiles if py... | Benedikt Tutzer | 2018-08-20 | 1 | -4/+2 |
| | * | | Added Wrappers for: | Benedikt Tutzer | 2018-08-13 | 1 | -1/+31 |
| | * | | added destructors for wires and cells | Benedikt Tutzer | 2018-07-10 | 1 | -0/+14 |
| | * | | removed debug output | Benedikt Tutzer | 2018-07-09 | 1 | -1/+0 |
| | * | | multiple designs can now exist independent from each other. Cells/Wires/Modul... | Benedikt Tutzer | 2018-07-09 | 1 | -0/+55 |
| * | | | Add "wbflip" command | Clifford Wolf | 2019-04-20 | 1 | -2/+5 |
| * | | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -3/+3 |
