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authorwhitequark <whitequark@whitequark.org>2019-06-19 05:22:13 +0000
committerwhitequark <whitequark@whitequark.org>2019-06-19 05:22:13 +0000
commitdf6576edc83817b692d2096e806bd822f3fda430 (patch)
treec49db07ad195a822f38fc8f91b59aa80b8d9607b /kernel/rtlil.cc
parent64947453e22404e570d670416ad66511a799e666 (diff)
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In RTLIL::Module::check(), check process invariants.
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r--kernel/rtlil.cc29
1 files changed, 28 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 790ba52a3..a09f4a0d1 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1381,7 +1381,34 @@ void RTLIL::Module::check()
for (auto &it : processes) {
log_assert(it.first == it.second->name);
log_assert(!it.first.empty());
- // FIXME: More checks here..
+ log_assert(it.second->root_case.compare.empty());
+ std::vector<CaseRule*> all_cases = {&it.second->root_case};
+ for (size_t i = 0; i < all_cases.size(); i++) {
+ for (auto &switch_it : all_cases[i]->switches) {
+ for (auto &case_it : switch_it->cases) {
+ for (auto &compare_it : case_it->compare) {
+ log_assert(switch_it->signal.size() == compare_it.size());
+ }
+ all_cases.push_back(case_it);
+ }
+ }
+ }
+ for (auto &sync_it : it.second->syncs) {
+ switch (sync_it->type) {
+ case SyncType::ST0:
+ case SyncType::ST1:
+ case SyncType::STp:
+ case SyncType::STn:
+ case SyncType::STe:
+ log_assert(!sync_it->signal.empty());
+ break;
+ case SyncType::STa:
+ case SyncType::STg:
+ case SyncType::STi:
+ log_assert(sync_it->signal.empty());
+ break;
+ }
+ }
}
for (auto &it : connections_) {