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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-024-505/+477
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| * kernel: pass-by-value into Design::scratchpad_set_string() tooEddie Hung2020-03-272-3/+3
| * kernel: const Wire* overload -> Wire* !!!Eddie Hung2020-03-261-1/+1
| * kernel: Cell::set{Port,Param}() to pass by value, but use std::moveEddie Hung2020-03-262-7/+7
| * kernel: SigSpec copies to not trigger pack()Eddie Hung2020-03-182-34/+5
| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-183-361/+355
| * kernel: speedupEddie Hung2020-03-181-30/+23
| * kernel: use const reference for SigSet tooEddie Hung2020-03-171-18/+18
| * kernel: fix DeleteWireWorkerEddie Hung2020-03-171-9/+4
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-132-38/+52
| * kernel: optimise Module::remove(const pool<RTLIL::Wire*>()Eddie Hung2020-03-122-10/+9
| * kernel: SigPool to use const& + overloads to prevent implicit SigSpecEddie Hung2020-03-121-19/+25
* | Merge pull request #1828 from YosysHQ/eddie/celltypes_speedupEddie Hung2020-04-011-10/+3
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| * | kernel: share a single CellTypes within a passEddie Hung2020-03-181-10/+3
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* | Clean up pseudo-private member usage in `kernel/yosys.cc`.Alberto Gonzalez2020-04-011-14/+13
* | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-272-1/+6
* | Update CopyrightClaire Wolf2020-03-161-1/+1
* | License: bump year and add titleWaldir Pimenta2020-03-141-1/+1
* | exclude clang from checkingMiodrag Milanovic2020-03-131-1/+1
* | Add YS_ prefix to macros, add explanation and apply to older version as wellMiodrag Milanovic2020-03-133-20/+23
* | Use boost xpressive for gcc 4.8Miodrag Milanovic2020-03-133-23/+29
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* Fix compilation for emccjiegec2020-03-112-1/+4
* Add ScriptPass::run_nocheck and use for abc9David Shah2020-03-092-0/+13
* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-2/+0
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| * Closes #1717. Add more precise Verilog source location information to AST and...Alberto Gonzalez2020-02-231-2/+0
* | Small fixesEddie Hung2020-02-271-2/+2
* | Fixes for older compilersEddie Hung2020-02-271-1/+8
* | Make TimingInfo::TimingInfo(SigBit) constructor explicitEddie Hung2020-02-271-4/+5
* | TimingInfo: index by (port_name,offset)Eddie Hung2020-02-271-9/+19
* | Fix spacingEddie Hung2020-02-271-50/+50
* | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-3/+4
* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-1/+4
* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-18/+2
* | abc9_ops: add and use new TimingInfo structEddie Hung2020-02-271-0/+173
* | Merge pull request #1705 from YosysHQ/logger_passMiodrag Milanović2020-02-263-2/+100
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| * Remove duplicate warning detectionMiodrag Milanovic2020-02-231-0/+6
| * Handle expect no warnings together with expectedMiodrag Milanovic2020-02-223-4/+12
| * Prevent double error messageMiodrag Milanovic2020-02-171-1/+3
| * Option to expect no warningsMiodrag Milanovic2020-02-173-0/+5
| * No new error if already failingMiodrag Milanovic2020-02-171-1/+2
| * remove whitespaceMiodrag Milanovic2020-02-141-1/+1
| * Add expect option to logger commandMiodrag Milanovic2020-02-143-2/+78
* | specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-2/+6
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* Merge pull request #1659 from YosysHQ/clifford/experimentalClaire Wolf2020-01-295-3/+55
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| * Improve logging use of experimental featuresClaire Wolf2020-01-283-4/+8
| * Add log_experimental() and experimental() API and "yosys -x"Claire Wolf2020-01-275-3/+51
* | Add and use SigSpec::reverse()Eddie Hung2020-01-281-0/+2
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* Merge pull request #1613 from porglezomp-misc/version-flag-aliasClaire Wolf2020-01-271-0/+6
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| * Add --version and -version as aliases for -VCassie Jones2020-01-051-0/+6
* | As before, only display MEM if Linux or FreeBSDEddie Hung2020-01-141-3/+7
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