| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2017-10-10 | 1 | -16/+5 |
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| | * | Remove some dead code | Clifford Wolf | 2017-10-10 | 1 | -15/+0 |
| | * | Allow $past, $stable, $rose, $fell in $global_clock blocks | Clifford Wolf | 2017-10-10 | 1 | -1/+5 |
| * | | Start work on pre-processor for Verific SVA properties | Clifford Wolf | 2017-10-10 | 1 | -10/+153 |
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| * | Improve handling of Verific errors | Clifford Wolf | 2017-10-05 | 1 | -11/+9 |
| * | Improve Verific error handling, check VHDL static asserts | Clifford Wolf | 2017-10-04 | 1 | -11/+25 |
| * | Fix nasty bug in Verific bindings | Clifford Wolf | 2017-10-04 | 1 | -1/+1 |
| * | Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys | Clifford Wolf | 2017-10-03 | 2 | -14/+14 |
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| | * | Turned a few member functions into const, esp. dumpAst(), dumpVlog(). | Udi Finkelstein | 2017-09-30 | 2 | -14/+14 |
| * | | Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textboo... | Udi Finkelstein | 2017-09-30 | 1 | -3/+5 |
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| * | Allow $size and $bits in verilog mode, actually check test case | Clifford Wolf | 2017-09-29 | 1 | -1/+1 |
| * | $size() now works correctly for all cases! | Udi Finkelstein | 2017-09-26 | 1 | -17/+17 |
| * | $size() seems to work now with or without the optional parameter. | Udi Finkelstein | 2017-09-26 | 1 | -10/+40 |
| * | enable $bits() and $size() functions only when the SystemVerilog flag is enab... | Udi Finkelstein | 2017-09-26 | 1 | -1/+1 |
| * | Added $bits() for memories as well. | Udi Finkelstein | 2017-09-26 | 1 | -2/+26 |
| * | $size() now works with memories as well! | Udi Finkelstein | 2017-09-26 | 1 | -1/+3 |
| * | Add $size() function. At the moment it works only on expressions, not on memo... | Udi Finkelstein | 2017-09-26 | 1 | -0/+14 |
| * | Increase maximum LUT size in blifparse to 12 bits | Clifford Wolf | 2017-09-27 | 1 | -1/+1 |
| * | Parse reals as string in JSON front-end | Clifford Wolf | 2017-09-26 | 1 | -0/+28 |
| * | Minor coding style fix | Clifford Wolf | 2017-09-26 | 1 | -1/+1 |
| * | Merge branch 'master' of https://github.com/combinatorylogic/yosys into combi... | Clifford Wolf | 2017-09-26 | 1 | -41/+69 |
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| | * | Adding support for string macros and macros with arguments after include | combinatorylogic | 2017-09-21 | 1 | -41/+69 |
| * | | Fix ignoring of simulation timings so that invalid module parameters cause sy... | Clifford Wolf | 2017-09-26 | 2 | -4/+2 |
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| * | json: Parse inout correctly rather than as an output | Robert Ou | 2017-08-14 | 1 | -0/+1 |
| * | Add merging of "past FFs" to verific importer | Clifford Wolf | 2017-07-29 | 1 | -2/+76 |
| * | Add minimal support for PSL in VHDL via Verific | Clifford Wolf | 2017-07-28 | 1 | -19/+155 |
| * | Improve Verific HDL language options | Clifford Wolf | 2017-07-28 | 1 | -4/+4 |
| * | Fix handling of non-user-declared Verific netbus | Clifford Wolf | 2017-07-28 | 1 | -2/+3 |
| * | Improve Verific SVA importer | Clifford Wolf | 2017-07-27 | 1 | -0/+34 |
| * | Add log_warning_noprefix() API, Use for Verific warnings and errors | Clifford Wolf | 2017-07-27 | 1 | -1/+1 |
| * | Add "verific -import -n" and "verific -import -nosva" | Clifford Wolf | 2017-07-27 | 1 | -14/+36 |
| * | Improve Verific SVA import: negedge and $past | Clifford Wolf | 2017-07-27 | 1 | -6/+49 |
| * | Improve Verific SVA importer | Clifford Wolf | 2017-07-27 | 1 | -37/+58 |
| * | Improve Verific bindings (mostly related to SVA) | Clifford Wolf | 2017-07-26 | 1 | -110/+320 |
| * | Improve "help verific" message | Clifford Wolf | 2017-07-25 | 1 | -5/+5 |
| * | Add "verific -extnets" | Clifford Wolf | 2017-07-25 | 1 | -23/+130 |
| * | Improve "verific -all" handling | Clifford Wolf | 2017-07-25 | 1 | -26/+45 |
| * | Add "verific -import -d <dump_file" | Clifford Wolf | 2017-07-24 | 1 | -6/+35 |
| * | Add "verific -import -flatten" and "verific -import -v" | Clifford Wolf | 2017-07-24 | 1 | -107/+164 |
| * | Add "verific -import -k" | Clifford Wolf | 2017-07-22 | 1 | -42/+51 |
| * | Improve docs for verific bindings, add simply sby example | Clifford Wolf | 2017-07-22 | 5 | -48/+89 |
| * | Fix "read_blif -wideports" handling of cells with wide ports | Clifford Wolf | 2017-07-21 | 1 | -3/+33 |
| * | Add a paragraph about pre-defined macros to read_verilog help message | Clifford Wolf | 2017-07-21 | 1 | -0/+4 |
| * | Add attributes and parameter support to JSON front-end | Clifford Wolf | 2017-07-10 | 1 | -7/+50 |
| * | Add JSON front-end | Clifford Wolf | 2017-07-08 | 2 | -0/+472 |
| * | Add Verific Release information to log | Clifford Wolf | 2017-07-04 | 1 | -0/+12 |
| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons... | Clifford Wolf | 2017-06-07 | 2 | -0/+8 |
| * | Fix handling of Verilog ~& and ~| operators | Clifford Wolf | 2017-06-01 | 1 | -0/+8 |
| * | Add support for localparam in module header | Clifford Wolf | 2017-04-30 | 1 | -1/+7 |
| * | Add support for `resetall compiler directive | Clifford Wolf | 2017-04-26 | 1 | -0/+7 |
