aboutsummaryrefslogtreecommitdiffstats
path: root/frontends
Commit message (Expand)AuthorAgeFilesLines
* verilog: Fix const eval of unbased unsized constantsJannis Harder2023-04-201-1/+1
* verilog: Support void functionsJannis Harder2023-03-202-1/+19
* verific: Fix enum_values support and signed attribute valuesJannis Harder2023-03-151-34/+33
* Merge pull request #3682 from daglem/struct-member-out-of-boundsJannis Harder2023-03-104-21/+69
|\
| * Index struct/union members within corresponding wire chunksDag Lem2023-03-054-32/+67
| * Out of bounds checking for struct/union membersDag Lem2023-02-191-5/+18
* | Handle more wide case selector typesMiodrag Milanovic2023-02-271-14/+42
|/
* Support for data and array queries on struct/union item expressionsDag Lem2023-02-151-12/+49
* Merge pull request #3661 from daglem/struct-array-range-offsetJannis Harder2023-02-151-22/+31
|\
| * Handle range offsets in packed arrays within packed structsDag Lem2023-02-051-22/+31
* | Resolve package types in interfaces (#3658)Dag Lem2023-02-121-3/+3
* | For case select values use Sa instead of Sx and SzMiodrag Milanovic2023-02-082-5/+42
* | Add verific import support for OPER_WIDE_CASE_SELECT_BOXMiodrag Milanovic2023-02-061-0/+41
|/
* Resolve struct member package typesDag Lem2023-01-291-0/+7
* Handle struct members of union type (#3641)Dag Lem2023-01-292-2/+2
* Fixes for some of clang scan-build detected issuesMiodrag Milanovic2023-01-174-9/+11
* print filename in liberty log_headerN. Engelhardt2023-01-111-2/+2
* Merge pull request #3467 from jix/fix_cellarray_simplifyJannis Harder2022-12-191-0/+2
|\
| * simplify: Do not recursively simplify AST_CELL within AST_CELLARRAYJannis Harder2022-12-071-0/+2
* | respect noblackbox attribute in verificMiodrag Milanovic2022-12-151-0/+6
* | Merge pull request #3573 from daglem/struct-array-multidimensionalJannis Harder2022-12-071-98/+78
|\ \ | |/ |/|
| * Made make_struct_member_range side-effect-free againDag Lem2022-12-041-20/+20
| * Support for packed multidimensional arrays within packed structsDag Lem2022-12-031-98/+78
* | Merge pull request #3568 from YosysHQ/verific_msgMiodrag Milanović2022-12-051-3/+16
|\ \
| * | set VERI-1063 explicitlyMiodrag Milanovic2022-12-021-5/+7
| * | Set all verific messages of certain type to otherMiodrag Milanovic2022-11-301-3/+14
* | | Merge pull request #3569 from YosysHQ/ver_no_rewritersMiodrag Milanović2022-12-051-0/+2
|\ \ \ | |_|/ |/| |
| * | reset elaboration error after rewriterMiodrag Milanovic2022-11-301-0/+2
| |/
* | Merge pull request #3551 from daglem/struct-array-swapped-rangeJannis Harder2022-12-012-21/+61
|\ \ | |/ |/|
| * Added asserts for current limitation of array dimensions in packed structsDag Lem2022-11-301-0/+8
| * Check for all cases of currently unsupported array dimensions in packed structsDag Lem2022-11-301-10/+13
| * Support for swapped ranges in second array dimensionDag Lem2022-11-231-3/+10
| * Support for arrays with swapped ranges within structsDag Lem2022-11-122-10/+32
* | update documentationMiodrag Milanovic2022-11-251-3/+3
* | Support importing verilog configurations using VerificMiodrag Milanovic2022-11-252-4/+39
* | Merge pull request #3552 from daglem/fix-sv-c-array-dimensionsJannis Harder2022-11-231-3/+3
|\ \
| * | Correct interpretation of SystemVerilog C-style array dimensionsDag Lem2022-11-131-3/+3
* | | Merge branch 'zachjs-master'Jannis Harder2022-11-211-0/+4
|\ \ \ | |/ / |/| |
| * | verilog: Support module-scoped task/function callsZachary Snow2022-10-291-0/+4
* | | Add additional help infoMiodrag Milanovic2022-10-311-0/+2
* | | Enable importing blackbox modules onlyMiodrag Milanovic2022-10-311-1/+33
* | | Support for reading liberty files using verificMiodrag Milanovic2022-10-311-1/+45
|/ /
* | Skip verific primitives and operators import by defaultMiodrag Milanovic2022-10-141-0/+1
* | Add option to import all cells from all librariesMiodrag Milanovic2022-10-141-1/+30
* | fix whitespaceMiodrag Milanovic2022-10-101-1/+1
* | Merge pull request #3452 from ALGCDG/masterMiodrag Milanović2022-10-101-1/+8
|\ \
| * | Changing error reason string to be based on lut input plane limit constant.Archie2022-10-021-1/+1
| * | Adding check for BLIF names command input plane size.Archie2022-08-211-1/+8
* | | Fix handling of verific -L options, add implicit "-L work"Claire Xenia Wolf2022-10-101-0/+14
* | | Add support for EDIF file reading using VerificMiodrag Milanovic2022-10-041-1/+47
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 07:22:48 +0000