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| author | Clifford Wolf <clifford@clifford.at> | 2017-06-01 12:43:21 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-06-01 12:43:21 +0200 |
| commit | 129984e115d318e00ec065ea76cb8c5926393bc4 (patch) | |
| tree | ab29b5dc3b1cddc386e3f4653a31c96f65562cc0 /frontends | |
| parent | 0290b68a44b815cb852393ebcb16b1e15948a90e (diff) | |
| download | yosys-129984e115d318e00ec065ea76cb8c5926393bc4.tar.gz yosys-129984e115d318e00ec065ea76cb8c5926393bc4.tar.bz2 yosys-129984e115d318e00ec065ea76cb8c5926393bc4.zip | |
Fix handling of Verilog ~& and ~| operators
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 26201d618..154b59ebc 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1537,10 +1537,18 @@ basic_expr: $$ = new AstNode(AST_BIT_AND, $1, $4); append_attr($$, $3); } | + basic_expr OP_NAND attr basic_expr { + $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4)); + append_attr($$, $3); + } | basic_expr '|' attr basic_expr { $$ = new AstNode(AST_BIT_OR, $1, $4); append_attr($$, $3); } | + basic_expr OP_NOR attr basic_expr { + $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4)); + append_attr($$, $3); + } | basic_expr '^' attr basic_expr { $$ = new AstNode(AST_BIT_XOR, $1, $4); append_attr($$, $3); |