| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Update ABC to hg rev 6283c5d99b06 | Clifford Wolf | 2017-10-11 | 1 | -1/+1 |
| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2017-10-10 | 28 | -211/+234 |
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| | * | Rewrite ABC output to include proper net names in timing report | Clifford Wolf | 2017-10-10 | 1 | -2/+17 |
| | * | Add timing constraints to osu035 example | Clifford Wolf | 2017-10-10 | 3 | -2/+4 |
| | * | Remove some dead code | Clifford Wolf | 2017-10-10 | 1 | -15/+0 |
| | * | Allow $past, $stable, $rose, $fell in $global_clock blocks | Clifford Wolf | 2017-10-10 | 1 | -1/+5 |
| | * | Add $shiftx support to verilog front-end | Clifford Wolf | 2017-10-07 | 1 | -0/+17 |
| | * | Update ABC to hg rev 0fc1803a77c0 | Clifford Wolf | 2017-10-06 | 1 | -1/+1 |
| | * | Clean whitespace and permissions in techlibs/intel | Larry Doolittle | 2017-10-05 | 21 | -190/+190 |
| * | | Start work on pre-processor for Verific SVA properties | Clifford Wolf | 2017-10-10 | 1 | -10/+153 |
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| * | Improve handling of Verific errors | Clifford Wolf | 2017-10-05 | 1 | -11/+9 |
| * | Improve Verific error handling, check VHDL static asserts | Clifford Wolf | 2017-10-04 | 1 | -11/+25 |
| * | Add blackbox command | Clifford Wolf | 2017-10-04 | 2 | -0/+82 |
| * | Fix nasty bug in Verific bindings | Clifford Wolf | 2017-10-04 | 1 | -1/+1 |
| * | Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys | Clifford Wolf | 2017-10-03 | 2 | -14/+14 |
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| | * | Turned a few member functions into const, esp. dumpAst(), dumpVlog(). | Udi Finkelstein | 2017-09-30 | 2 | -14/+14 |
| * | | Merge branch 'fix_shift_reduce_conflict' of https://github.com/udif/yosys | Clifford Wolf | 2017-10-03 | 1 | -3/+5 |
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| | * | | Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textboo... | Udi Finkelstein | 2017-09-30 | 1 | -3/+5 |
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| * | | Merge branch 'dh73-master' | Clifford Wolf | 2017-10-03 | 31 | -729/+2965 |
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| | * | Rename "write_verilog -nobasenradix" to "write_verilog -decimal" | Clifford Wolf | 2017-10-03 | 2 | -20/+14 |
| | * | Tested and working altsyncarm without init files | dh73 | 2017-10-01 | 2 | -57/+59 |
| | * | Fixed wrong declaration in Verilog backend | dh73 | 2017-10-01 | 1 | -3/+3 |
| | * | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ... | dh73 | 2017-10-01 | 31 | -730/+2970 |
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| * | Add first draft of eASIC back-end | Clifford Wolf | 2017-09-29 | 2 | -0/+191 |
| * | Fix synth_ice40 doc regarding -top default | Clifford Wolf | 2017-09-29 | 1 | -1/+1 |
| * | Allow $size and $bits in verilog mode, actually check test case | Clifford Wolf | 2017-09-29 | 3 | -1/+3 |
| * | Merge pull request #425 from udif/udif_dollar_bits | Clifford Wolf | 2017-09-29 | 2 | -1/+103 |
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| | * | $size() now works correctly for all cases! | Udi Finkelstein | 2017-09-26 | 2 | -22/+28 |
| | * | $size() seems to work now with or without the optional parameter. | Udi Finkelstein | 2017-09-26 | 2 | -18/+58 |
| | * | enable $bits() and $size() functions only when the SystemVerilog flag is enab... | Udi Finkelstein | 2017-09-26 | 1 | -1/+1 |
| | * | Added $bits() for memories as well. | Udi Finkelstein | 2017-09-26 | 2 | -8/+31 |
| | * | $size() now works with memories as well! | Udi Finkelstein | 2017-09-26 | 2 | -3/+7 |
| | * | Add $size() function. At the moment it works only on expressions, not on memo... | Udi Finkelstein | 2017-09-26 | 2 | -0/+29 |
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| * | Merge pull request #421 from stephengroat/osx-travis | Clifford Wolf | 2017-09-28 | 3 | -2/+12 |
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| | * | delete bad backslash | Stephen | 2017-09-27 | 1 | -1/+1 |
| | * | forgot to install bundles | Stephen | 2017-09-27 | 1 | -0/+1 |
| | * | Add osx tests using brew bundle | Stephen Groat | 2017-09-27 | 3 | -2/+11 |
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| * | Increase maximum LUT size in blifparse to 12 bits | Clifford Wolf | 2017-09-27 | 1 | -1/+1 |
| * | Parse reals as string in JSON front-end | Clifford Wolf | 2017-09-26 | 1 | -0/+28 |
| * | Merge branch 'vlogpp-inc-fixes' | Clifford Wolf | 2017-09-26 | 1 | -41/+69 |
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| | * | Minor coding style fix | Clifford Wolf | 2017-09-26 | 1 | -1/+1 |
| | * | Merge branch 'master' of https://github.com/combinatorylogic/yosys into combi... | Clifford Wolf | 2017-09-26 | 1 | -41/+69 |
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| | * | Adding support for string macros and macros with arguments after include | combinatorylogic | 2017-09-21 | 1 | -41/+69 |
| * | | Fix ignoring of simulation timings so that invalid module parameters cause sy... | Clifford Wolf | 2017-09-26 | 2 | -4/+2 |
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| * | Merge pull request #413 from azonenberg/extract-reduce-tweaks | Clifford Wolf | 2017-09-16 | 1 | -86/+170 |
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| | * | Added missing "break" | Andrew Zonenberg | 2017-09-15 | 1 | -0/+1 |
| | * | Implemented off-chain support for extract_reduce | Andrew Zonenberg | 2017-09-15 | 1 | -84/+157 |
| | * | extract_reduce now only removes the head of the chain, relying on "clean" to ... | Andrew Zonenberg | 2017-09-15 | 1 | -9/+19 |
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| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2017-09-15 | 1 | -2/+2 |
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| | * | Merge pull request #412 from azonenberg/reduce-fixes | Clifford Wolf | 2017-09-14 | 1 | -2/+2 |
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