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| * SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-222-4/+4
| | | | | | | | created interim RTLIL::SigSpec::chunks_rw()
| * SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-228-120/+120
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| * SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-228-120/+120
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| * Added "autoidx" statement to ilang file formatClifford Wolf2014-07-211-1/+14
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| * Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog ↵Clifford Wolf2014-07-201-17/+21
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| * Added support for $bu0 to verilog backendClifford Wolf2014-07-201-0/+16
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| * Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-131-0/+1
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| * Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-071-18/+17
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| * Added $lut support to blif backend (by user eddiehung from reddit)Clifford Wolf2014-02-221-0/+23
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| * Better handling of nameDef and nameRef in edif backendClifford Wolf2014-02-211-21/+27
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| * Fixed instantiating multi-bit ports in edif backendClifford Wolf2014-02-211-2/+4
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| * Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-211-17/+65
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* | fixed memory next issue, when same memory is written in different case statementahmedirfan19832014-09-181-8/+27
| | | | | | | | fixed reduce_xnor, logic_not bug translation bug
* | added $pmux cell translationAhmed Irfan2014-09-021-2/+38
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* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-122-6/+6
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* disabling splice command in the scriptAhmed Irfan2014-02-112-2/+6
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* register output correctedAhmed Irfan2014-02-111-1/+1
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* added concat and slice cell translationAhmed Irfan2014-02-113-36/+59
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* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+22
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* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-061-1/+1
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* Added BTOR backend README fileClifford Wolf2014-02-052-1/+24
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* Added support for dump -appendClifford Wolf2014-02-041-3/+12
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-032-1/+6
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* Merge branch 'btor' of https://github.com/ahmedirfan1983/yosysClifford Wolf2014-01-261-1/+5
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| * root bug correctedAhmed Irfan2014-01-251-1/+5
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* | beautified write_intersynthJohann Glaser2014-01-251-0/+9
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* removed regex includeAhmed Irfan2014-01-241-1/+0
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* merged clifford changes + removed regexAhmed Irfan2014-01-241-26/+52
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* Use techmap -share_map in btor scriptsClifford Wolf2014-01-242-2/+2
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* Moved btor scripts to backends/btor/Clifford Wolf2014-01-242-0/+50
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* slice bug correctedAhmed Irfan2014-01-201-1/+1
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* assert featureAhmed Irfan2014-01-201-9/+40
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* verilog default options pullAhmed Irfan2014-01-171-28/+97
| | | | shift operator width issues
* slice error correctedAhmed Irfan2014-01-161-5/+5
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* width issuesAhmed Irfan2014-01-151-64/+87
| | | | dff cell for more than one registers
* BTOR backendAhmed Irfan2014-01-141-274/+328
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* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-032-7/+9
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| * Updated manual/command-reference-manual.texClifford Wolf2013-12-281-1/+1
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| * Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-271-6/+8
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* | btorAhmed Irfan2014-01-032-0/+774
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-042-2/+2
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-043-18/+24
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* Fixed gentb_constant handling in autotest backendClifford Wolf2013-12-041-2/+2
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* Added dump -m and -n optionsClifford Wolf2013-11-292-54/+89
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* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-241-4/+6
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* Added support for signed parameters in ilangClifford Wolf2013-11-241-1/+1
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* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-241-2/+0
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* Added modelsim support to autotestClifford Wolf2013-11-241-6/+6
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* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-243-0/+15
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* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-225-14/+14
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