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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
| commit | 369bf81a7049c96f62af084bb5007fbf45e36ab4 (patch) | |
| tree | 92071580c9bd60888ee5861d59457947a8adfde7 /backends | |
| parent | ecc30255ba70910777a4586f5bd6abc818073293 (diff) | |
| download | yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.tar.gz yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.tar.bz2 yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.zip | |
Added support for non-const === and !== (for miter circuits)
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index ff41c2e3c..d8160c97b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -506,12 +506,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) HANDLE_BINOP("$sshl", "<<<") HANDLE_BINOP("$sshr", ">>>") - HANDLE_BINOP("$lt", "<") - HANDLE_BINOP("$le", "<=") - HANDLE_BINOP("$eq", "==") - HANDLE_BINOP("$ne", "!=") - HANDLE_BINOP("$ge", ">=") - HANDLE_BINOP("$gt", ">") + HANDLE_BINOP("$lt", "<") + HANDLE_BINOP("$le", "<=") + HANDLE_BINOP("$eq", "==") + HANDLE_BINOP("$ne", "!=") + HANDLE_BINOP("$eqx", "===") + HANDLE_BINOP("$nex", "!==") + HANDLE_BINOP("$ge", ">=") + HANDLE_BINOP("$gt", ">") HANDLE_BINOP("$add", "+") HANDLE_BINOP("$sub", "-") |