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author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:29:11 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:29:11 +0100 |
commit | f71e27dbf15d063ca45378ff2eb2d8102220f199 (patch) | |
tree | 67137e2ddf4dcf588fa4397d15d3e7648805a896 /backends | |
parent | 609caa23b5e12547c043dc4a1827d1a531af1992 (diff) | |
download | yosys-f71e27dbf15d063ca45378ff2eb2d8102220f199.tar.gz yosys-f71e27dbf15d063ca45378ff2eb2d8102220f199.tar.bz2 yosys-f71e27dbf15d063ca45378ff2eb2d8102220f199.zip |
Remove auto_wire framework (smarter than the verilog standard)
Diffstat (limited to 'backends')
-rw-r--r-- | backends/ilang/ilang_backend.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index 513e57fa7..b51b3f88b 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -118,8 +118,6 @@ void ILANG_BACKEND::dump_wire(FILE *f, std::string indent, const RTLIL::Wire *wi fprintf(f, "\n"); } fprintf(f, "%s" "wire ", indent.c_str()); - if (wire->auto_width) - fprintf(f, "auto "); if (wire->width != 1) fprintf(f, "width %d ", wire->width); if (wire->start_offset != 0) |