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author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
commit | 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d (patch) | |
tree | 9a847fc2fc608ce9ffbc947bcb18eea2205bb2d5 /backends | |
parent | 7bffde6abdaf6fc2ed090946442f90b2438e6126 (diff) | |
download | yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.tar.gz yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.tar.bz2 yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.zip |
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
Diffstat (limited to 'backends')
-rw-r--r-- | backends/btor/btor.cc | 4 | ||||
-rw-r--r-- | backends/verilog/verilog_backend.cc | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 7853160e2..9139749c0 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -45,9 +45,9 @@ struct BtorDumperConfig struct WireInfo { RTLIL::IdString cell_name; - RTLIL::SigChunk *chunk; + const RTLIL::SigChunk *chunk; - WireInfo(RTLIL::IdString c, RTLIL::SigChunk* ch) : cell_name(c), chunk(ch) { } + WireInfo(RTLIL::IdString c, const RTLIL::SigChunk* ch) : cell_name(c), chunk(ch) { } }; struct WireInfoOrder diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 4b60f0fbd..160835087 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -149,7 +149,7 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) return true; } -void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false) +void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false) { if (width < 0) width = data.bits.size() - offset; @@ -203,7 +203,7 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo } } -void dump_sigchunk(FILE *f, RTLIL::SigChunk &chunk, bool no_decimal = false) +void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = false) { if (chunk.wire == NULL) { dump_const(f, chunk.data, chunk.width, chunk.offset, no_decimal); |