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| author | Ahmed Irfan <irfan@ubuntu.(none)> | 2014-02-11 13:28:05 +0100 |
|---|---|---|
| committer | Ahmed Irfan <irfan@ubuntu.(none)> | 2014-02-11 13:28:05 +0100 |
| commit | 1d64b3e0084814774cb2a0eb5a9c99dbe1101bc2 (patch) | |
| tree | f6464f70acdd2757c23db29f6e48a6c4bda9bb8e /backends | |
| parent | 1a2dc48c2ab8a809e345e1e62cc3f81fe7fd9485 (diff) | |
| download | yosys-1d64b3e0084814774cb2a0eb5a9c99dbe1101bc2.tar.gz yosys-1d64b3e0084814774cb2a0eb5a9c99dbe1101bc2.tar.bz2 yosys-1d64b3e0084814774cb2a0eb5a9c99dbe1101bc2.zip | |
register output corrected
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/btor/btor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 2c8546f05..03ef183a5 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -647,7 +647,7 @@ struct BtorDumper log(" - width is %d\n", output_width); int cond = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\CLK")), 1); bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool(); - const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\D")); + const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\Q")); int value = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\D")), output_width); unsigned start_bit = 0; for(unsigned i=0; i<cell_output->chunks.size(); ++i) |