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* write_xaiger to use original bit for co, not sigmap()-ed bitEddie Hung2019-02-211-3/+6
* Remove swap fileEddie Hung2019-02-201-0/+0
* write_aiger: fix CI/CO and symbolsEddie Hung2019-02-202-7/+13
* write_xaiger to not write latches, CO/PO fixesEddie Hung2019-02-201-17/+26
* Merge branch 'master' into xaigEddie Hung2019-02-192-66/+218
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| * Instead of INIT param on cells, use initial statement with hier ref asEddie Hung2019-02-171-18/+13
| * Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-172-86/+246
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| | * Removed unused variables, functions.Jim Lawson2019-02-151-20/+0
| | * Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-151-48/+225
* | | CleanupEddie Hung2019-02-161-4/+5
* | | CleanupEddie Hung2019-02-161-2/+1
* | | write_xaiger to support non-bit cell connections, and cope with COs for -OEddie Hung2019-02-161-13/+15
* | | write_aiger -O to write dummy output as __dummy_o__Eddie Hung2019-02-161-2/+5
* | | Tidy up write_xaigerEddie Hung2019-02-161-8/+6
* | | write_aiger() to perform CI/CO post-processing and fix symbolsEddie Hung2019-02-161-7/+17
* | | Fixes needed for DFF circuitsEddie Hung2019-02-151-4/+3
* | | write_xaiger to cope with unknown cells by transforming them to CI/COEddie Hung2019-02-151-6/+44
* | | More cleanupEddie Hung2019-02-141-15/+6
* | | More cleanup of write_xaigerEddie Hung2019-02-141-73/+1
* | | Get rid of formal stuff from xaiger backendEddie Hung2019-02-141-58/+0
* | | Merge remote-tracking branch 'origin/read_aiger' into xaigEddie Hung2019-02-131-1/+1
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| * | Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
* | | Merge https://github.com/YosysHQ/yosys into xaigEddie Hung2019-02-131-38/+41
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| * | Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
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| | * | write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
* | | | Add write_xaigerEddie Hung2019-02-112-21/+11
* | | | Copy backends/aiger/aiger.cc to xaiger.ccEddie Hung2019-02-081-0/+788
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* | | RefactorEddie Hung2019-02-061-21/+5
* | | write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
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* / Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::...Clifford Wolf2019-02-061-1/+1
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* Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
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| * write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
* | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-024-7/+7
* Squelch a little more trailing whitespaceLarry Doolittle2018-12-291-3/+3
* Minor style fixesClifford Wolf2018-12-182-1/+1
* Add btor ops for $mul, $div, $mod and $concatmakaimann2018-12-172-2/+38
* write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-1/+1
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| * write_verilog: add a missing newline.whitequark2018-12-161-1/+1
* | Merge pull request #729 from whitequark/write_verilog_initialClifford Wolf2018-12-161-0/+2
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| * | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
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* | Add yosys-smtbmc support for btor witnessClifford Wolf2018-12-101-15/+100
* | Add "yosys-smtbmc --btorwit" skeletonClifford Wolf2018-12-081-1/+19
* | Fix btor init value handlingClifford Wolf2018-12-081-9/+13
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* Add "write_aiger -I -O -B"Clifford Wolf2018-11-121-2/+36
* Merge pull request #693 from YosysHQ/rlimitClifford Wolf2018-11-071-8/+11
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| * Limit stack size to 16 MB on DarwinClifford Wolf2018-11-071-1/+4
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