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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-13 14:09:36 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-13 14:09:36 -0800 |
| commit | f0f5d8a5cc44c8b89d234ab9cac20f294a821271 (patch) | |
| tree | dfa43819f273a0d5ec391fdcc2ba9ba013a12da9 /backends | |
| parent | 06cf0555ee0b28948295d8c9aedd2583c16ecc6a (diff) | |
| parent | c23e3f07517d4818d9ab1b532250353492cf50c2 (diff) | |
| download | yosys-f0f5d8a5cc44c8b89d234ab9cac20f294a821271.tar.gz yosys-f0f5d8a5cc44c8b89d234ab9cac20f294a821271.tar.bz2 yosys-f0f5d8a5cc44c8b89d234ab9cac20f294a821271.zip | |
Merge remote-tracking branch 'origin/read_aiger' into xaig
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index a1b1ecd66..4b5a13941 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1251,7 +1251,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str()); std::string init; - if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { + if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) { std::stringstream ss; dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */); init = ss.str(); |