diff options
| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-15 15:22:18 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-15 15:22:18 -0800 |
| commit | 486a2704156c51e1331e69cd5160965a1ef73506 (patch) | |
| tree | d5af1ae38c8c55237e735832fe23e169c328f124 /backends | |
| parent | a786ac4d5351e4e8eae0e6abf7577cd330b2a232 (diff) | |
| download | yosys-486a2704156c51e1331e69cd5160965a1ef73506.tar.gz yosys-486a2704156c51e1331e69cd5160965a1ef73506.tar.bz2 yosys-486a2704156c51e1331e69cd5160965a1ef73506.zip | |
Fixes needed for DFF circuits
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 433f1cdd6..27e156a98 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -137,7 +137,7 @@ struct XAigerWriter if (bit.wire == nullptr) { if (wire->port_output) { aig_map[wirebit] = (bit == State::S1) ? 1 : 0; - output_bits.insert(wirebit); + //output_bits.insert(wirebit); } continue; } @@ -220,8 +220,7 @@ struct XAigerWriter } else if (cell->output(c.first)) { SigBit O = sigmap(b); - if (!w->port_output) - ci_bits.insert(O); + ci_bits.insert(O); undriven_bits.erase(O); } else log_abort(); @@ -525,7 +524,7 @@ struct XAigerWriter input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire)); } - if (wire->port_output || co_bits.count(RTLIL::SigBit{wire, i})) { + if (output_bits.count(RTLIL::SigBit{wire, i}) || co_bits.count(RTLIL::SigBit{wire, i})) { int o = ordered_outputs.at(sig[i]); output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire)); } |