diff options
author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-14 13:27:26 -0800 |
---|---|---|
committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-14 13:27:26 -0800 |
commit | afa4389445adc8e53871af78ab1c38c98e03a6fc (patch) | |
tree | c55899980ee38ef391e77a82ef938765e87df710 /backends | |
parent | 323dd0e608b38116db1e2bcda1ebc4ba98823990 (diff) | |
download | yosys-afa4389445adc8e53871af78ab1c38c98e03a6fc.tar.gz yosys-afa4389445adc8e53871af78ab1c38c98e03a6fc.tar.bz2 yosys-afa4389445adc8e53871af78ab1c38c98e03a6fc.zip |
Get rid of formal stuff from xaiger backend
Diffstat (limited to 'backends')
-rw-r--r-- | backends/aiger/xaiger.cc | 58 |
1 files changed, 0 insertions, 58 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 7fc61fa9a..c5cede3b1 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -205,64 +205,6 @@ struct XAigerWriter continue; } - if (cell->type == "$assert") - { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); - unused_bits.erase(A); - unused_bits.erase(EN); - asserts.push_back(make_pair(A, EN)); - continue; - } - - if (cell->type == "$assume") - { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); - unused_bits.erase(A); - unused_bits.erase(EN); - assumes.push_back(make_pair(A, EN)); - continue; - } - - if (cell->type == "$live") - { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); - unused_bits.erase(A); - unused_bits.erase(EN); - liveness.push_back(make_pair(A, EN)); - continue; - } - - if (cell->type == "$fair") - { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); - unused_bits.erase(A); - unused_bits.erase(EN); - fairness.push_back(make_pair(A, EN)); - continue; - } - - if (cell->type == "$anyconst") - { - for (auto bit : sigmap(cell->getPort("\\Y"))) { - undriven_bits.erase(bit); - ff_map[bit] = bit; - } - continue; - } - - if (cell->type == "$anyseq") - { - for (auto bit : sigmap(cell->getPort("\\Y"))) { - undriven_bits.erase(bit); - input_bits.insert(bit); - } - continue; - } - log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell)); } |