| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | sv: auto add nosync to certain always_comb local vars | Zachary Snow | 2022-01-07 | 1 | -0/+3 | |
| | | | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated. | |||||
| * | sv: fix size cast internal expression extension | Zachary Snow | 2022-01-07 | 1 | -0/+2 | |
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| * | sv: fix size cast clipping expression width | Zachary Snow | 2022-01-03 | 1 | -0/+2 | |
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| * | fix width detection of array querying function in case and case item expressions | Zachary Snow | 2021-12-17 | 1 | -0/+2 | |
| | | | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`. | |||||
| * | Next dev cycle | Miodrag Milanovic | 2021-12-03 | 1 | -0/+3 | |
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| * | Release version 0.12 | Miodrag Milanovic | 2021-12-03 | 1 | -1/+1 | |
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| * | Update CHANGELOG and CODEOWNERS | Miodrag Milanovic | 2021-12-01 | 1 | -0/+21 | |
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| * | Next dev cycle | Miodrag Milanovic | 2021-11-05 | 1 | -0/+3 | |
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| * | Release version 0.11 | Miodrag Milanovic | 2021-11-05 | 1 | -1/+1 | |
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| * | Add missing changelog item | Miodrag Milanovic | 2021-11-05 | 1 | -0/+1 | |
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| * | Add missing items in CHANGELOG | Miodrag Milanovic | 2021-10-29 | 1 | -0/+6 | |
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| * | verilog: use derived module info to elaborate cell connections | Zachary Snow | 2021-10-25 | 1 | -0/+8 | |
| | | | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change | |||||
| * | Add $aldff and $aldffe: flip-flops with async load. | Marcelina Kościelnicka | 2021-10-02 | 1 | -0/+2 | |
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| * | Prepare for next release cycle | Miodrag Milanovic | 2021-09-27 | 1 | -1/+4 | |
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| * | sv: support wand and wor of data types | Zachary Snow | 2021-09-21 | 1 | -1/+2 | |
| | | | | | | | This enables the usage of declarations of wand or wor with a base type of logic, integer, or a typename. Note that declarations of nets with 2-state base types is still permitted, in violation of the spec. | |||||
| * | Updates for CHANGELOG (#2997) | Miodrag Milanović | 2021-09-13 | 1 | -48/+126 | |
| | | | | Added missing changes from git log and group items | |||||
| * | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 1 | -0/+5 | |
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| * | memory: Introduce $meminit_v2 cell, with EN input. | Marcelina Kościelnicka | 2021-07-28 | 1 | -0/+1 | |
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| * | Replace opt_rmdff with opt_dff. | Marcelina Kościelnicka | 2020-08-07 | 1 | -1/+1 | |
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| * | techmap: Add _TECHMAP_CELLNAME_ special parameter. | Marcelina Kościelnicka | 2020-07-21 | 1 | -1/+2 | |
| | | | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells. | |||||
| * | Add dfflegalize pass. | Marcelina Kościelnicka | 2020-07-01 | 1 | -0/+2 | |
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| * | Update CHANGELOG | Xiretza | 2020-05-28 | 1 | -0/+1 | |
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| * | Update CHANGELOG and manual for departure from upstream | Eddie Hung | 2020-04-27 | 1 | -2/+2 | |
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| * | select: add select -unset option | Eddie Hung | 2020-04-16 | 1 | -0/+1 | |
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| * | kernel: add design -delete option | Eddie Hung | 2020-04-16 | 1 | -0/+1 | |
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| * | Get rid of dffsr2dff. | Marcelina Kościelnicka | 2020-04-15 | 1 | -0/+1 | |
| | | | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed. | |||||
| * | Add to changelog | Miodrag Milanovic | 2020-02-17 | 1 | -0/+1 | |
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| * | Merge branch 'master' into master | Rodrigo A. Melo | 2020-02-03 | 1 | -0/+1 | |
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| | * | Add opt_lut_ins pass. (#1673) | Marcelina Kościelnicka | 2020-02-03 | 1 | -0/+1 | |
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| * | | Merge branch 'master' of https://github.com/YosysHQ/yosys | Rodrigo Alejandro Melo | 2020-02-03 | 1 | -1/+3 | |
| |\| | | | | | | | | | | | Solved a conflict into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | |||||
| | * | Update CHANGELOG and README | David Shah | 2020-02-02 | 1 | -0/+1 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | Removed a line jump into the CHANGELOG | Rodrigo Alejandro Melo | 2020-02-01 | 1 | -3/+2 | |
| | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | |||||
| * | | $readmem[hb] file inclusion is now relative to the Verilog file | Rodrigo Alejandro Melo | 2020-01-31 | 1 | -1/+2 | |
| |/ | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | |||||
| * | Add 'abc9 -dff' to CHANGELOG | Eddie Hung | 2020-01-02 | 1 | -0/+1 | |
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| * | Add CHANGELOG entry, add abc9_{flop,keep} attr to README.md | Eddie Hung | 2019-12-30 | 1 | -0/+1 | |
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| * | Add "scratchpad" to CHANGELOG | Eddie Hung | 2019-12-18 | 1 | -0/+1 | |
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| * | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 1 | -0/+1 | |
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| * | xilinx: Improve flip-flop handling. | Marcin Kościelnicki | 2019-12-18 | 1 | -0/+2 | |
| | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. | |||||
| * | Update CHANGELOG and README | David Shah | 2019-11-22 | 1 | -0/+2 | |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | Add "check -mapped" | Clifford Wolf | 2019-10-02 | 1 | -0/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | synth_xilinx: Support latches, remove used-up FF init values. | Marcin Kościelnicki | 2019-09-30 | 1 | -0/+1 | |
| | | | | | Fixes #1387. | |||||
| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-20 | 1 | -0/+2 | |
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| | * | Update CHANGELOG | Clifford Wolf | 2019-09-20 | 1 | -0/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 1 | -0/+1 | |
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| | * | Added extractinv pass | Marcin Kościelnicki | 2019-09-19 | 1 | -0/+1 | |
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| * | | Add more entries | Eddie Hung | 2019-09-19 | 1 | -0/+1 | |
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| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-12 | 1 | -0/+1 | |
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| | * | Add -match-init option to dff2dffs. | Marcin Kościelnicki | 2019-09-11 | 1 | -0/+1 | |
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| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-11 | 1 | -0/+1 | |
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| | * | techmap: Add support for extracting init values of ports | Marcin Kościelnicki | 2019-09-07 | 1 | -0/+1 | |
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index : iCE40/yosys | |
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