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authorRodrigo Alejandro Melo <rodrigomelo9@gmail.com>2020-02-01 22:48:03 -0300
committerRodrigo Alejandro Melo <rodrigomelo9@gmail.com>2020-02-01 22:56:01 -0300
commit2774aae0f2395e121457a666dc16bedb4c3bba06 (patch)
tree1390b4b93008bc7f7f5cfce5eaf777885316e305 /CHANGELOG
parenteaaba6e09132c07b85bdae418a2b7f46b57e019e (diff)
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Removed a line jump into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
Diffstat (limited to 'CHANGELOG')
-rw-r--r--CHANGELOG5
1 files changed, 2 insertions, 3 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 4abfeec06..a908096e3 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -53,13 +53,12 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added support for flip-flops with synchronous reset to synth_xilinx
- Added support for flip-flops with reset and enable to synth_xilinx
- Added "check -mapped"
- - Added checking of SystemVerilog always block types (always_comb,
- always_latch and always_ff)
+ - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff)
- Added "xilinx_dffopt" pass
- Added "scratchpad" pass
- Added "abc9 -dff"
- Added "synth_xilinx -dff"
- - Improved support of $readmem[hb] file inclusion which is now relative to the Verilog file
+ - Improved support of $readmem[hb] Memory Content File inclusion
Yosys 0.8 .. Yosys 0.9
----------------------