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| author | Marcin Kościelnicki <koriakin@0x04.net> | 2019-08-16 03:14:03 +0000 |
|---|---|---|
| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2019-09-07 16:30:43 +0200 |
| commit | a82e8df7d37c02258d36223bb16833331dc8808e (patch) | |
| tree | e9040059a57e535dd426eeae443d1cde2fba3be6 /CHANGELOG | |
| parent | de8adecd396cfd83c198a525813cb255eb74bdfa (diff) | |
| download | yosys-a82e8df7d37c02258d36223bb16833331dc8808e.tar.gz yosys-a82e8df7d37c02258d36223bb16833331dc8808e.tar.bz2 yosys-a82e8df7d37c02258d36223bb16833331dc8808e.zip | |
techmap: Add support for extracting init values of ports
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -38,6 +38,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Improvements in pmgen: slices, choices, define, generate - Added "xilinx_srl" for Xilinx shift register extraction - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl") + - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass Yosys 0.8 .. Yosys 0.9 ---------------------- |