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* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-071-0/+3
* sv: fix size cast internal expression extensionZachary Snow2022-01-071-0/+2
* sv: fix size cast clipping expression widthZachary Snow2022-01-031-0/+2
* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-171-0/+2
* Next dev cycleMiodrag Milanovic2021-12-031-0/+3
* Release version 0.12Miodrag Milanovic2021-12-031-1/+1
* Update CHANGELOG and CODEOWNERSMiodrag Milanovic2021-12-011-0/+21
* Next dev cycleMiodrag Milanovic2021-11-051-0/+3
* Release version 0.11Miodrag Milanovic2021-11-051-1/+1
* Add missing changelog itemMiodrag Milanovic2021-11-051-0/+1
* Add missing items in CHANGELOGMiodrag Milanovic2021-10-291-0/+6
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-0/+8
* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-021-0/+2
* Prepare for next release cycleMiodrag Milanovic2021-09-271-1/+4
* sv: support wand and wor of data typesZachary Snow2021-09-211-1/+2
* Updates for CHANGELOG (#2997)Miodrag Milanović2021-09-131-48/+126
* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-0/+5
* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-281-0/+1
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-1/+1
* techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-1/+2
* Add dfflegalize pass.Marcelina Kościelnicka2020-07-011-0/+2
* Update CHANGELOGXiretza2020-05-281-0/+1
* Update CHANGELOG and manual for departure from upstreamEddie Hung2020-04-271-2/+2
* select: add select -unset optionEddie Hung2020-04-161-0/+1
* kernel: add design -delete optionEddie Hung2020-04-161-0/+1
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-0/+1
* Add to changelogMiodrag Milanovic2020-02-171-0/+1
* Merge branch 'master' into masterRodrigo A. Melo2020-02-031-0/+1
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| * Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+1
* | Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-031-1/+3
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| * Update CHANGELOG and READMEDavid Shah2020-02-021-0/+1
* | Removed a line jump into the CHANGELOGRodrigo Alejandro Melo2020-02-011-3/+2
* | $readmem[hb] file inclusion is now relative to the Verilog fileRodrigo Alejandro Melo2020-01-311-1/+2
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* Add 'abc9 -dff' to CHANGELOGEddie Hung2020-01-021-0/+1
* Add CHANGELOG entry, add abc9_{flop,keep} attr to README.mdEddie Hung2019-12-301-0/+1
* Add "scratchpad" to CHANGELOGEddie Hung2019-12-181-0/+1
* xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-181-0/+1
* xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-181-0/+2
* Update CHANGELOG and READMEDavid Shah2019-11-221-0/+2
* Add "check -mapped"Clifford Wolf2019-10-021-0/+1
* synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-301-0/+1
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-201-0/+2
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| * Update CHANGELOGClifford Wolf2019-09-201-0/+2
* | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-191-0/+1
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| * Added extractinv passMarcin Kościelnicki2019-09-191-0/+1
* | Add more entriesEddie Hung2019-09-191-0/+1
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-121-0/+1
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| * Add -match-init option to dff2dffs.Marcin Kościelnicki2019-09-111-0/+1
* | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-111-0/+1
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| * techmap: Add support for extracting init values of portsMarcin Kościelnicki2019-09-071-0/+1
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