| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #1414 from hzeller/improve-replace-with-empty-map | Eddie Hung | 2019-09-29 | 1 | -0/+2 |
| |\ | | | | | Avoid work in replace() if rules empty. | ||||
| | * | Avoid work in replace() if rules empty. | Henner Zeller | 2019-09-29 | 1 | -0/+2 |
| | | | | | | | | | | | | | | | This speeds up processing when number of bits are large but there is actually nothing to replace. Adresses part of #1382. Signed-off-by: Henner Zeller <h.zeller@acm.org> | ||||
| * | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 44 | -281/+6234 |
| |\ \ | | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5) | ||||
| | * | | Re-order | Eddie Hung | 2019-09-27 | 2 | -2/+2 |
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| | * | | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
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| | * | | Ooops AREG and BREG to default to -1 | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
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| | * | | Update doc with max cascade chain of 20 | Eddie Hung | 2019-09-26 | 1 | -2/+4 |
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| | * | | Do not always zero out C (e.g. during cascade breaks) | Eddie Hung | 2019-09-26 | 2 | -7/+3 |
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| | * | | Update doc | Eddie Hung | 2019-09-26 | 1 | -1/+2 |
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| | * | | Zero out ports | Eddie Hung | 2019-09-26 | 1 | -2/+2 |
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| | * | | xilinx_dsp_cascade to also cascade AREG and BREG | Eddie Hung | 2019-09-26 | 2 | -454/+172 |
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| | * | | Try recursive pmgen for P cascade | Eddie Hung | 2019-09-26 | 1 | -88/+118 |
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| | * | | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once | Eddie Hung | 2019-09-26 | 1 | -9/+4 |
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| | * | | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 |
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| | * | | CREG to check for \keep | Eddie Hung | 2019-09-26 | 1 | -0/+3 |
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| | * | | Remove newline | Eddie Hung | 2019-09-26 | 1 | -1/+0 |
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| | * | | select once | Eddie Hung | 2019-09-26 | 2 | -8/+12 |
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| | * | | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 3 | -38/+14 |
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| | * | | mul2dsp.v slice names | Eddie Hung | 2019-09-25 | 1 | -5/+5 |
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| | * | | Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed) | Eddie Hung | 2019-09-25 | 1 | -1/+5 |
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| | * | | Reject if (* init *) present | Eddie Hung | 2019-09-25 | 2 | -0/+6 |
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| | * | | Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit | Eddie Hung | 2019-09-25 | 1 | -3/+1 |
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| | * | | Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" | Eddie Hung | 2019-09-25 | 1 | -2/+6 |
| | | | | | | | | | | | | | This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1. | ||||
| | * | | Revert "No need for $__mul anymore?" | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
| | | | | | | | | | | | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827. | ||||
| | * | | Rework xilinx_dsp postAdd for new wreduce call | Eddie Hung | 2019-09-25 | 1 | -3/+3 |
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| | * | | Only wreduce on t:$add | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
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| | * | | Remove _TECHMAP_CELLTYPE_ check since all $mul | Eddie Hung | 2019-09-25 | 1 | -6/+2 |
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| | * | | Fix memory issue since SigSpec& could be invalidated | Eddie Hung | 2019-09-25 | 1 | -6/+10 |
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| | * | | No need for $__mul anymore? | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
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| | * | | unextend only used in init | Eddie Hung | 2019-09-25 | 1 | -2/+1 |
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| | * | | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 2 | -5/+5 |
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| | * | | Oops. Actually use __NAME__ in ABC_DSP48E1 macro | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
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| | * | | Add (* techmap_autopurge *) to abc_unmap.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 |
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| | * | | "abc_padding" attr for blackbox outputs that were padded, remove them later | Eddie Hung | 2019-09-23 | 2 | -4/+22 |
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| | * | | Force $inout.out ports to begin with '$' to indicate internal | Eddie Hung | 2019-09-23 | 2 | -3/+3 |
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| | * | | Add techmap_autopurge to outputs in abc_map.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 |
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| | * | | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 3 | -87/+0 |
| | | | | | | | | | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405. | ||||
| | * | | Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" | Eddie Hung | 2019-09-23 | 1 | -38/+38 |
| | | | | | | | | | | | | | This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b. | ||||
| | * | | Revert "Vivado does not like zero width port connections" | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
| | | | | | | | | | | | | | This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98. | ||||
| | * | | Vivado does not like zero width port connections | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
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| | * | | Remove (* techmap_autopurge *) from abc_unmap.v since no effect | Eddie Hung | 2019-09-23 | 1 | -38/+38 |
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| | * | | Add a xilinx_finalise pass | Eddie Hung | 2019-09-23 | 3 | -0/+87 |
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| | * | | Set [AB]CASCREG to legal values | Eddie Hung | 2019-09-23 | 1 | -6/+10 |
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| | * | | Comment to explain separating CREG packing | Eddie Hung | 2019-09-23 | 1 | -0/+8 |
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| | * | | Separate out CREG packing into new pattern, to avoid conflict with PREG | Eddie Hung | 2019-09-23 | 4 | -46/+273 |
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| | * | | Move log_debug("\n") later | Eddie Hung | 2019-09-23 | 1 | -1/+1 |
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| | * | | Move unextend initialisation later | Eddie Hung | 2019-09-23 | 1 | -12/+9 |
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| | * | | Use new port() overload once more | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
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| | * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-23 | 2 | -1/+69 |
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| | * | | | Grammar | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
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index : iCE40/yosys | |
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