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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 22:58:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 22:58:03 -0700 |
| commit | f1de93edf5b5c73440d445d8d6fa32251d2bdab1 (patch) | |
| tree | aa244105f95faefe8544024340111c791c0c6e52 | |
| parent | cd8a640989d0819266d2678304951de2a247405d (diff) | |
| download | yosys-f1de93edf5b5c73440d445d8d6fa32251d2bdab1.tar.gz yosys-f1de93edf5b5c73440d445d8d6fa32251d2bdab1.tar.bz2 yosys-f1de93edf5b5c73440d445d8d6fa32251d2bdab1.zip | |
Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 0a345e88d..3d0b1f2c3 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -53,6 +53,10 @@ code sigA sigB sigC sigD sigM clock } else sigM = P; + // This sigM could have no users if downstream $add + // is narrower than $mul result, for example + if (sigM.empty()) + reject; clock = port(dsp, \CLK, SigBit()); endcode @@ -261,7 +265,7 @@ endcode match postAdd // Ensure that Z mux is not already used - if port(dsp, \OPMODE).extract(4,3).is_fully_zero() + if port(dsp, \OPMODE, SigSpec()).extract(4,3).is_fully_zero() select postAdd->type.in($add) select GetSize(port(postAdd, \Y)) <= 48 |