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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 19:04:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 19:04:07 -0700 |
| commit | 895e2befa76bd326cc47fd40de112ea067fcaf98 (patch) | |
| tree | f6fa017d4e6944f27eb861f618f0cfc2d5606249 | |
| parent | 67c2db3486a7b2ff34f89dc861fb66d51ba6101b (diff) | |
| download | yosys-895e2befa76bd326cc47fd40de112ea067fcaf98.tar.gz yosys-895e2befa76bd326cc47fd40de112ea067fcaf98.tar.bz2 yosys-895e2befa76bd326cc47fd40de112ea067fcaf98.zip | |
Vivado does not like zero width port connections
| -rw-r--r-- | techlibs/xilinx/xilinx_finalise.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/xilinx_finalise.cc b/techlibs/xilinx/xilinx_finalise.cc index db73babe3..2c0bd3534 100644 --- a/techlibs/xilinx/xilinx_finalise.cc +++ b/techlibs/xilinx/xilinx_finalise.cc @@ -53,7 +53,7 @@ struct XilinxFinalisePass : public Pass for (auto cell : module->selected_cells()) { if (cell->type != ID(DSP48E1)) continue; - for (auto &conn : cell->connections_) { + for (auto conn : cell->connections()) { if (!cell->output(conn.first)) continue; bool purge = true; @@ -74,7 +74,7 @@ struct XilinxFinalisePass : public Pass if (purge) { log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second)); - conn.second = SigSpec(); + cell->unsetPort(conn.first); } } } |