iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #1414 from hzeller/improve-replace-with-empty-map	Eddie Hung	2019-09-29	1	-0/+2
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\| *	Avoid work in replace() if rules empty.	Henner Zeller	2019-09-29	1	-0/+2
* \|	Merge pull request #1359 from YosysHQ/xc7dsp	Eddie Hung	2019-09-29	44	-281/+6234
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\| * \|	Re-order	Eddie Hung	2019-09-27	2	-2/+2
\| * \|	Missing (* mul2dsp *) for sliceB	Eddie Hung	2019-09-27	1	-2/+2
\| * \|	Ooops AREG and BREG to default to -1	Eddie Hung	2019-09-27	1	-2/+2
\| * \|	Update doc with max cascade chain of 20	Eddie Hung	2019-09-26	1	-2/+4
\| * \|	Do not always zero out C (e.g. during cascade breaks)	Eddie Hung	2019-09-26	2	-7/+3
\| * \|	Update doc	Eddie Hung	2019-09-26	1	-1/+2
\| * \|	Zero out ports	Eddie Hung	2019-09-26	1	-2/+2
\| * \|	xilinx_dsp_cascade to also cascade AREG and BREG	Eddie Hung	2019-09-26	2	-454/+172
\| * \|	Try recursive pmgen for P cascade	Eddie Hung	2019-09-26	1	-88/+118
\| * \|	Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once	Eddie Hung	2019-09-26	1	-9/+4
\| * \|	Typo	Eddie Hung	2019-09-26	1	-1/+1
\| * \|	CREG to check for \keep	Eddie Hung	2019-09-26	1	-0/+3
\| * \|	Remove newline	Eddie Hung	2019-09-26	1	-1/+0
\| * \|	select once	Eddie Hung	2019-09-26	2	-8/+12
\| * \|	Stop trying to be too smart by prematurely optimising	Eddie Hung	2019-09-26	3	-38/+14
\| * \|	mul2dsp.v slice names	Eddie Hung	2019-09-25	1	-5/+5
\| * \|	Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)	Eddie Hung	2019-09-25	1	-1/+5
\| * \|	Reject if (* init *) present	Eddie Hung	2019-09-25	2	-0/+6
\| * \|	Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit	Eddie Hung	2019-09-25	1	-3/+1
\| * \|	Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"	Eddie Hung	2019-09-25	1	-2/+6
\| * \|	Revert "No need for $__mul anymore?"	Eddie Hung	2019-09-25	1	-8/+8
\| * \|	Rework xilinx_dsp postAdd for new wreduce call	Eddie Hung	2019-09-25	1	-3/+3
\| * \|	Only wreduce on t:$add	Eddie Hung	2019-09-25	1	-1/+1
\| * \|	Remove _TECHMAP_CELLTYPE_ check since all $mul	Eddie Hung	2019-09-25	1	-6/+2
\| * \|	Fix memory issue since SigSpec& could be invalidated	Eddie Hung	2019-09-25	1	-6/+10
\| * \|	No need for $__mul anymore?	Eddie Hung	2019-09-25	1	-8/+8
\| * \|	unextend only used in init	Eddie Hung	2019-09-25	1	-2/+1
\| * \|	Call 'wreduce' after mul2dsp to avoid unextend()	Eddie Hung	2019-09-25	2	-5/+5
\| * \|	Oops. Actually use __NAME__ in ABC_DSP48E1 macro	Eddie Hung	2019-09-25	1	-1/+1
\| * \|	Add (* techmap_autopurge *) to abc_unmap.v too	Eddie Hung	2019-09-23	1	-11/+11
\| * \|	"abc_padding" attr for blackbox outputs that were padded, remove them later	Eddie Hung	2019-09-23	2	-4/+22
\| * \|	Force $inout.out ports to begin with '$' to indicate internal	Eddie Hung	2019-09-23	2	-3/+3
\| * \|	Add techmap_autopurge to outputs in abc_map.v too	Eddie Hung	2019-09-23	1	-11/+11
\| * \|	Revert "Add a xilinx_finalise pass"	Eddie Hung	2019-09-23	3	-87/+0
\| * \|	Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"	Eddie Hung	2019-09-23	1	-38/+38
\| * \|	Revert "Vivado does not like zero width port connections"	Eddie Hung	2019-09-23	1	-2/+2
\| * \|	Vivado does not like zero width port connections	Eddie Hung	2019-09-23	1	-2/+2
\| * \|	Remove (* techmap_autopurge *) from abc_unmap.v since no effect	Eddie Hung	2019-09-23	1	-38/+38
\| * \|	Add a xilinx_finalise pass	Eddie Hung	2019-09-23	3	-0/+87
\| * \|	Set [AB]CASCREG to legal values	Eddie Hung	2019-09-23	1	-6/+10
\| * \|	Comment to explain separating CREG packing	Eddie Hung	2019-09-23	1	-0/+8
\| * \|	Separate out CREG packing into new pattern, to avoid conflict with PREG	Eddie Hung	2019-09-23	4	-46/+273
\| * \|	Move log_debug("\n") later	Eddie Hung	2019-09-23	1	-1/+1
\| * \|	Move unextend initialisation later	Eddie Hung	2019-09-23	1	-12/+9
\| * \|	Use new port() overload once more	Eddie Hung	2019-09-23	1	-2/+2
\| * \|	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-09-23	2	-1/+69
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\| * \| \|	Grammar	Eddie Hung	2019-09-20	1	-1/+1