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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 13:26:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 13:26:34 -0700 |
| commit | d0dbbc26054d1cd7b8766e2d996196e246216e8c (patch) | |
| tree | a73b34a2d33ff33d93adf5223d8df5ec4cc0f477 | |
| parent | a67af3d5e5fd584837f55d2d97d621299e4fdf0c (diff) | |
| download | yosys-d0dbbc26054d1cd7b8766e2d996196e246216e8c.tar.gz yosys-d0dbbc26054d1cd7b8766e2d996196e246216e8c.tar.bz2 yosys-d0dbbc26054d1cd7b8766e2d996196e246216e8c.zip | |
Move unextend initialisation later
| -rw-r--r-- | passes/pmgen/xilinx_dsp_cascade.pmg | 21 |
1 files changed, 9 insertions, 12 deletions
diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index 19fe48bba..37674efea 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -3,7 +3,15 @@ pattern xilinx_dsp_cascadeP udata <std::function<SigSpec(const SigSpec&)>> unextend state <SigSpec> sigC -code +match dsp_pcin + select dsp_pcin->type.in(\DSP48E1) + select !param(dsp_pcin, \CREG, State::S1).as_bool() + select port(dsp_pcin, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011") + select nusers(port(dsp_pcin, \C, SigSpec())) > 1 + select nusers(port(dsp_pcin, \PCIN, SigSpec())) == 0 +endmatch + +code sigC unextend = [](const SigSpec &sig) { int i; for (i = GetSize(sig)-1; i > 0; i--) @@ -14,17 +22,6 @@ code ++i; return sig.extract(0, i); }; -endcode - -match dsp_pcin - select dsp_pcin->type.in(\DSP48E1) - select !param(dsp_pcin, \CREG, State::S1).as_bool() - select port(dsp_pcin, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011") - select nusers(port(dsp_pcin, \C, SigSpec())) > 1 - select nusers(port(dsp_pcin, \PCIN, SigSpec())) == 0 -endmatch - -code sigC sigC = unextend(port(dsp_pcin, \C)); endcode |